X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fls1012aqds.h;h=9498a03f405b0af745e2953c01cc8d26d4bf7dec;hb=f9a48654ee70fbad29f487d074fd36a1548b4209;hp=fa1ed73719d21f5bb1b24fcdca7fa08c617e9cf5;hpb=9e0bb4c1d9560cf8af0657939d01d7da8ef0f342;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
index fa1ed73..9498a03 100644
--- a/include/configs/ls1012aqds.h
+++ b/include/configs/ls1012aqds.h
@@ -1,7 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2016 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #ifndef __LS1012AQDS_H__
@@ -12,12 +11,7 @@
 /* DDR */
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
 #define CONFIG_CHIP_SELECTS_PER_CTRL	1
-#define CONFIG_NR_DRAM_BANKS		2
 #define CONFIG_SYS_SDRAM_SIZE		0x40000000
-#define CONFIG_CMD_MEMINFO
-#define CONFIG_CMD_MEMTEST
-#define CONFIG_SYS_MEMTEST_START	0x80000000
-#define CONFIG_SYS_MEMTEST_END		0x9fffffff
 
 /*
  * QIXIS Definitions
@@ -58,11 +52,9 @@
 #define RTC
 #define CONFIG_RTC_PCF8563 1
 #define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
-#define CONFIG_CMD_DATE
 
 /* EEPROM */
 #define CONFIG_ID_EEPROM
-#define CONFIG_CMD_EEPROM
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #define CONFIG_SYS_EEPROM_BUS_NUM    0
 #define CONFIG_SYS_I2C_EEPROM_ADDR   0x57
@@ -79,9 +71,7 @@
 
 /* DSPI */
 #define CONFIG_FSL_DSPI1
-#define CONFIG_DEFAULT_SPI_BUS 1
 
-#define CONFIG_CMD_SPI
 #define MMAP_DSPI          DSPI1_BASE_ADDR
 
 #define CONFIG_SYS_DSPI_CTAR0   1
@@ -104,70 +94,14 @@
 				DSPI_CTAR_DT(0))
 #define CONFIG_SPI_FLASH_EON /* cs3 */
 
-#define CONFIG_SF_DEFAULT_SPEED      10000000
-#define CONFIG_SF_DEFAULT_MODE       SPI_MODE_0
-#define CONFIG_SF_DEFAULT_BUS        1
-#define CONFIG_SF_DEFAULT_CS         0
-
-/*
-* USB
-*/
-/* EHCI Support - disbaled by default */
-/*#define CONFIG_HAS_FSL_DR_USB*/
-
-#ifdef CONFIG_HAS_FSL_DR_USB
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#endif
-
-/*XHCI Support - enabled by default*/
-#define CONFIG_HAS_FSL_XHCI_USB
-
-#ifdef CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_MAX_CONTROLLER_COUNT         1
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
-#endif
-
 /*  MMC  */
 #ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
 #endif
 
-/* SATA */
-#define CONFIG_LIBATA
-#define	CONFIG_SCSI
-#define CONFIG_SCSI_AHCI
-#define CONFIG_SCSI_AHCI_PLAT
-#define CONFIG_CMD_SCSI
-#define CONFIG_DOS_PARTITION
-#define CONFIG_BOARD_LATE_INIT
-
-#define CONFIG_SYS_SATA				AHCI_BASE_ADDR
-
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
-#define CONFIG_SYS_SCSI_MAX_LUN			1
-#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
-						CONFIG_SYS_SCSI_MAX_LUN)
-#define CONFIG_PARTITION_UUIDS
-#define CONFIG_EFI_PARTITION
-#define CONFIG_CMD_GPT
-
 #define CONFIG_PCIE1		/* PCIE controller 1 */
 
-#define CONFIG_NET_MULTI
 #define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_CMD_PCI
-
-#define CONFIG_CMD_MEMINFO
-#define CONFIG_CMD_MEMTEST
-#define CONFIG_SYS_MEMTEST_START	0x80000000
-#define CONFIG_SYS_MEMTEST_END		0x9fffffff
-
-#define CONFIG_MISC_INIT_R
 
+#include <asm/fsl_secure_boot.h>
 #endif /* __LS1012AQDS_H__ */