X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fliteboard.h;h=6aba6a616eacb6da9bdece48353bf1008f1ed792;hb=b641dd3ec8dc3f6b18d2fa945ac3ab597063d191;hp=2ce39ffecf9018112482299921a98c2ce64bc5ae;hpb=79a34b71c943a80af5c6d9a2af736fbb37dcc14c;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h
index 2ce39ff..6aba6a6 100644
--- a/include/configs/liteboard.h
+++ b/include/configs/liteboard.h
@@ -1,10 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright (C) 2015 Freescale Semiconductor, Inc.
  * Copyright (C) 2016 Grinn
  *
  * Configuration settings for the Grinn liteBoard (i.MX6UL).
- *
- * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef __LITEBOARD_CONFIG_H
 #define __LITEBOARD_CONFIG_H
@@ -25,7 +24,6 @@
 /* MMC Configs */
 #ifdef CONFIG_FSL_USDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC1_BASE_ADDR
-#define CONFIG_SUPPORT_EMMC_BOOT
 #endif
 
 #define CONFIG_SYS_MMC_IMG_LOAD_PART	1
@@ -112,11 +110,7 @@
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
 #define CONFIG_SYS_HZ			1000
 
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_STACKSIZE		SZ_128K
-
 /* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
@@ -129,20 +123,12 @@
 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 
 /* FLASH and environment organization */
-#define CONFIG_ENV_SIZE			SZ_8K
-#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_ENV_OFFSET		(8 * SZ_64K)
 #define CONFIG_SYS_MMC_ENV_DEV		0
 #define CONFIG_SYS_MMC_ENV_PART		0
 #define CONFIG_MMCROOT			"/dev/mmcblk0p2"
 
-#define CONFIG_CMD_BMODE
-
 /* USB Configs */
 #ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_MX6
-#define CONFIG_USB_STORAGE
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_MXC_USB_FLAGS   0
@@ -151,16 +137,12 @@
 
 #ifdef CONFIG_CMD_NET
 #define CONFIG_FEC_MXC
-#define CONFIG_MII
 #define CONFIG_FEC_ENET_DEV		0
 
 #define IMX_FEC_BASE			ENET_BASE_ADDR
 #define CONFIG_FEC_MXC_PHYADDR		0x0
 #define CONFIG_FEC_XCV_TYPE		RMII
 #define CONFIG_ETHPRIME			"FEC"
-
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_SMSC
 #endif
 
 #define CONFIG_IMX_THERMAL