X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fkmeter1.h;h=bec08dab1fffa32dc6551dc8b41d00a3213513b0;hb=2a49bf3149e34e6f910e70bbc0a26e81cfdbdf70;hp=25b1c172e6c7367441f102df6bd59b75fff0c73e;hpb=833d94bcdc89cf88928be21587240950afdc33c8;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 25b1c17..bec08da 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -25,13 +25,15 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */ -#define CONFIG_MPC83XX 1 /* MPC83XX family */ +#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ #define CONFIG_KMETER1 1 /* KMETER1 board specific */ +#define CONFIG_HOSTNAME kmeter1 /* include common defines/options for all Keymile boards */ #include "keymile-common.h" +#define CONFIG_MISC_INIT_R 1 /* * System Clock Setup */ @@ -51,10 +53,11 @@ #define CONFIG_SYS_HRCW_HIGH (\ HRCWH_CORE_ENABLE | \ HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_NORMAL | \ + HRCWH_BOOTSEQ_DISABLE | \ HRCWH_SW_WATCHDOG_DISABLE | \ HRCWH_ROM_LOC_LOCAL_16BIT | \ HRCWH_BIG_ENDIAN | \ + HRCWH_LALE_EARLY | \ HRCWH_LDP_CLEAR ) /* @@ -91,8 +94,8 @@ * Manually set up DDR parameters */ #define CONFIG_DDR_II -#define CONFIG_SYS_DDR_SIZE 256 /* MB */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f +#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ CSCONFIG_ROW_BIT_13 | \ CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS) @@ -101,11 +104,12 @@ SDRAM_CFG_SREN) #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CONFIG_SYS_DDR_INTERVAL ((0x100 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ - (0x406 << SDRAM_INTERVAL_REFINT_SHIFT)) +#define CONFIG_SYS_DDR_INTERVAL ((0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x3cf << SDRAM_INTERVAL_REFINT_SHIFT)) -#define CONFIG_SYS_DDR_MODE 0x04440242 -#define CONFIG_SYS_DDR_MODE2 0x00800000 +#define CONFIG_SYS_DDRCDR 0x40000001 +#define CONFIG_SYS_DDR_MODE 0x47860452 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ @@ -116,22 +120,22 @@ (0 << TIMING_CFG0_WRT_SHIFT) | \ (0 << TIMING_CFG0_RWT_SHIFT)) -#define CONFIG_SYS_DDR_TIMING_1 (( TIMING_CFG1_CASLAT_40) | \ +#define CONFIG_SYS_DDR_TIMING_1 (( TIMING_CFG1_CASLAT_50) | \ ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \ - ( 1 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - ( 2 << TIMING_CFG1_WRREC_SHIFT) | \ - ( 2 << TIMING_CFG1_REFREC_SHIFT) | \ - ( 2 << TIMING_CFG1_ACTTORW_SHIFT) | \ - ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - ( 2 << TIMING_CFG1_PRETOACT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_2 ((5 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + ( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + ( 3 << TIMING_CFG1_WRREC_SHIFT) | \ + ( 7 << TIMING_CFG1_REFREC_SHIFT) | \ + ( 3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + ( 3 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ - (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ - (4 << TIMING_CFG2_CPO_SHIFT)) + (5 << TIMING_CFG2_CPO_SHIFT)) #define CONFIG_SYS_DDR_TIMING_3 0x00000000 @@ -141,9 +145,10 @@ #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ #define CONFIG_SYS_FLASH_BASE 0xF0000000 #define CONFIG_SYS_FLASH_BASE_1 0xF2000000 -#define CONFIG_SYS_PIGGY_BASE 0x80000000 +#define CONFIG_SYS_PIGGY_BASE 0xE8000000 +#define CONFIG_SYS_PIGGY_SIZE 128 #define CONFIG_SYS_PAXE_BASE 0xA0000000 -#define CONFIG_SYS_PAXE_SIZE 256 +#define CONFIG_SYS_PAXE_SIZE 512 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) #define CONFIG_SYS_RAMBOOT @@ -151,8 +156,7 @@ #undef CONFIG_SYS_RAMBOOT #endif -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ /* * Initial RAM Base Address Setup @@ -166,7 +170,9 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_2 | LCRR_CLKDIV_4) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_EADC LCRR_EADC_2 +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 /* * Init Local Bus Memory Controller: @@ -174,8 +180,8 @@ * Bank Bus Machine PortSz Size Device * ---- --- ------- ------ ----- ------ * 0 Local GPCM 16 bit 256MB FLASH - * 1 Local GPCM 8 bit 256KB GPIO/PIGGY - * 3 Local GPCM 8 bit 256MB PAXE + * 1 Local GPCM 8 bit 128MB GPIO/PIGGY + * 3 Local GPCM 8 bit 512MB PAXE * */ /* @@ -209,12 +215,12 @@ * PRIO1/PIGGY on the local bus CS1 */ #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_PIGGY_BASE /* Window base at flash base */ -#define CONFIG_SYS_LBLAWAR1_PRELIM 0x80000011 /* 256KB window size */ +#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001A /* 128MB window size */ #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_PIGGY_BASE | \ (1 << BR_PS_SHIFT) | /* 8 bit port size */ \ BR_V) -#define CONFIG_SYS_OR1_PRELIM (0xfffc0000 | /* 256KB */ \ +#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) | /* 128MB */ \ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ OR_GPCM_SCY_2 | \ OR_GPCM_TRLX | OR_GPCM_EAD) @@ -223,7 +229,7 @@ * PAXE on the local bus CS3 */ #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE /* Window base at flash base */ -#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001b /* 256MB window size */ +#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */ #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PAXE_BASE | \ (1 << BR_PS_SHIFT) | /* 8 bit port size */ \ @@ -286,7 +292,6 @@ #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#define CONFIG_ENV_SIZE 0x20000 #define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) /* Address and size of Redundant Environment Sector */ @@ -296,16 +301,43 @@ #else /* CFG_RAMBOOT */ #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ -#define CONFIG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) #define CONFIG_ENV_SIZE 0x2000 #endif /* CFG_RAMBOOT */ +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_FSL_I2C +#define CONFIG_SYS_I2C_SPEED 200000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_I2C_MULTI_BUS 1 +#define CONFIG_I2C_MUX 1 + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + +/* I2C SYSMON (LM75, AD7414 is almost compatible) */ +#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ +#define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */ +#define CONFIG_SYS_DTT_MAX_TEMP 70 +#define CONFIG_SYS_DTT_LOW_TEMP -30 +#define CONFIG_SYS_DTT_HYSTERESIS 3 +#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS) + +#if defined(CONFIG_CMD_NAND) +#define CONFIG_NAND_KMETER1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE CONFIG_SYS_PIGGY_BASE +#endif + #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI #endif #if defined(CFG_RAMBOOT) -#undef CONFIG_CMD_ENV +#undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif @@ -345,7 +377,7 @@ /* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PIGGY_BASE | BATU_BL_256K | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PIGGY_BASE | BATU_BL_128M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U @@ -365,7 +397,7 @@ /* PAXE: icache cacheable, but dcache-inhibit and guarded */ #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256K | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U @@ -401,57 +433,44 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define BOOTFLASH_START F0000000 + +#define CONFIG_PRAM 512 /* protected RAM [KBytes] */ + +#define MTDIDS_DEFAULT "nor2=app" +#define MTDPARTS_DEFAULT \ + "mtdparts=app:256k(u-boot),128k(env),128k(envred)," \ + "1536k(esw0),8704k(rootfs0),1536k(esw1),2432k(rootfs1),640k(var),768k(cfg)" + /* * Environment Configuration */ #define CONFIG_ENV_OVERWRITE - -#if defined(CONFIG_UEC_ETH) -#define CONFIG_HAS_ETH0 +#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ +#define CONFIG_KM_DEF_ENV "km-common=empty\0" #endif #define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ + CONFIG_KM_DEF_ENV \ "rootpath=/opt/eldk/ppc_82xx\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs}" \ - " console=ttyS0,${baudrate}\0" \ - "fdt_addr=f0080000\0" \ - "kernel_addr=f00a0000\0" \ - "ramdisk_addr=f03a0000\0" \ - "kernel_addr_r=400000\0" \ - "fdt_addr_r=800000\0" \ - "ramdisk_addr_r=810000\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${boot_file}; " \ - "tftp ${fdt_addr_r} ${fdt_file}; " \ - "run nfsargs addip addtty;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "fdt_file=/tftpboot/kmeter1/kmeter1.dtb\0" \ - "boot_file=/tftpboot/kmeter1/uImage\0" \ + "addcon=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ "ramdisk_file=/tftpboot/kmeter1/uRamdisk\0" \ - "u-boot=/tftpboot/kmeter1/u-boot.bin\0" \ - "loadaddr=" MK_STR(CONFIG_SYS_LOAD_ADDR) "\0" \ - "load=tftp $loadaddr ${u-boot}\0" \ - "update=protect off " MK_STR(TEXT_BASE) " +$filesize;" \ - "erase " MK_STR(TEXT_BASE) " +$filesize;" \ - "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize;" \ - "protect on " MK_STR(TEXT_BASE) " +$filesize;" \ - "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize;" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ "loadram=tftp ${ramdisk_addr_r} ${ramdisk_file}\0" \ "loadfdt=tftp ${fdt_addr_r} ${fdt_file}\0" \ - "loadkernel=tftp ${kernel_addr_r} ${boot_file}\0" \ + "loadkernel=tftp ${kernel_addr_r} ${bootfile}\0" \ "unlock=yes\0" \ + "fdt_addr=F0080000\0" \ + "kernel_addr=F00a0000\0" \ + "ramdisk_addr=F03a0000\0" \ + "ramdisk_addr_r=F10000\0" \ + "EEprom_ivm=pca9547:70:9\0" \ + "dtt_bus=pca9547:70:a\0" \ + "mtdids=nor0=app \0" \ + "mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0" \ "" +#if defined(CONFIG_UEC_ETH) +#define CONFIG_HAS_ETH0 +#endif + #endif /* __CONFIG_H */