X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fj721e_evm.h;h=a81496145c608b55e16fef38b88d31951c4cfe07;hb=10f6e4dc3a16c21f235416f975ecf2070ceb351f;hp=b707fc4e899fbf6eab53ebcfcac45d0b8ad5b83e;hpb=47e9c70421d75336336097c1425028b40e4f0b54;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h index b707fc4..a814961 100644 --- a/include/configs/j721e_evm.h +++ b/include/configs/j721e_evm.h @@ -10,7 +10,6 @@ #define __CONFIG_J721E_EVM_H #include -#include #include #include #include @@ -21,53 +20,25 @@ /* SPL Loader Configuration */ #if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \ - CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE) #define CONFIG_SYS_UBOOT_BASE 0x50280000 /* Image load address in RAM for DFU boot*/ #else #define CONFIG_SYS_UBOOT_BASE 0x50080000 -/* - * Maximum size in memory allocated to the SPL BSS. Keep it as tight as - * possible (to allow the build to go through), as this directly affects - * our memory footprint. The less we use for BSS the more we have available - * for everything else. - */ -#define CONFIG_SPL_BSS_MAX_SIZE 0xA000 -/* - * Link BSS to be within SPL in a dedicated region located near the top of - * the MCU SRAM, this way making it available also before relocation. Note - * that we are not using the actual top of the MCU SRAM as there is a memory - * location filled in by the boot ROM that we want to read out without any - * interference from the C context. - */ -#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX -\ - CONFIG_SPL_BSS_MAX_SIZE) -/* Set the stack right below the SPL BSS section */ -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_BSS_START_ADDR -/* Configure R5 SPL post-relocation malloc pool in DDR */ -#define CONFIG_SYS_SPL_MALLOC_START 0x84000000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M -/* Image load address in RAM for DFU boot*/ #endif -#ifdef CONFIG_SYS_K3_SPL_ATF -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin" -#endif - -#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE - #define CONFIG_SYS_BOOTM_LEN SZ_64M -#define CONFIG_CQSPI_REF_CLK 133333333 /* HyperFlash related configuration */ -#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 /* U-Boot general configuration */ #define EXTRA_ENV_J721E_BOARD_SETTINGS \ "default_device_tree=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ "findfdt=" \ "setenv name_fdt ${default_device_tree};" \ + "if test $board_name = j721e; then " \ + "setenv name_fdt k3-j721e-common-proc-board.dtb; fi;" \ + "if test $board_name = j721e-eaik || test $board_name = j721e-sk; then " \ + "setenv name_fdt k3-j721e-sk.dtb; fi;" \ "setenv fdtfile ${name_fdt}\0" \ "name_kern=Image\0" \ "console=ttyS2,115200n8\0" \ @@ -83,8 +54,6 @@ #ifdef CONFIG_SYS_K3_SPL_ATF #if defined(CONFIG_TARGET_J721E_R5_EVM) #define EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC \ - "addr_mainr5f0_0load=0x88000000\0" \ - "name_mainr5f0_0fw=/lib/firmware/j7-main-r5f0_0-fw\0" \ "addr_mcur5f0_0load=0x89000000\0" \ "name_mcur5f0_0fw=/lib/firmware/j7-mcu-r5f0_0-fw\0" #elif defined(CONFIG_TARGET_J7200_R5_EVM) @@ -122,7 +91,32 @@ "partitions=" PARTS_DEFAULT /* Set the default list of remote processors to boot */ -#if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM) +#if defined(CONFIG_TARGET_J7200_A72_EVM) +#define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY \ + "do_main_cpsw0_qsgmii_phyinit=1\0" \ + "init_main_cpsw0_qsgmii_phy=gpio set gpio@22_17;" \ + "gpio clear gpio@22_16\0" \ + "main_cpsw0_qsgmii_phyinit=" \ + "if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1 && test ${dorprocboot} -eq 1 && " \ + "test ${boot} = mmc; then " \ + "run init_main_cpsw0_qsgmii_phy;" \ + "fi;\0" +#ifdef DEFAULT_RPROCS +#undef DEFAULT_RPROCS +#endif +#elif defined(CONFIG_TARGET_J721E_A72_EVM) +#define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY \ + "init_main_cpsw0_qsgmii_phy=gpio set gpio@22_17;" \ + "gpio clear gpio@22_16\0" \ + "main_cpsw0_qsgmii_phyinit=" \ + "if test $board_name = J721EX-PM1-SOM || test $board_name = J721EX-PM2-SOM " \ + "|| test $board_name = j721e; then " \ + "do_main_cpsw0_qsgmii_phyinit=1; else " \ + "do_main_cpsw0_qsgmii_phyinit=0; fi;" \ + "if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1 && test ${dorprocboot} -eq 1 && " \ + "test ${boot} = mmc; then " \ + "run init_main_cpsw0_qsgmii_phy;" \ + "fi;\0" #ifdef DEFAULT_RPROCS #undef DEFAULT_RPROCS #endif @@ -130,6 +124,7 @@ #ifdef CONFIG_TARGET_J721E_A72_EVM #define DEFAULT_RPROCS "" \ + "2 /lib/firmware/j7-main-r5f0_0-fw " \ "3 /lib/firmware/j7-main-r5f0_1-fw " \ "4 /lib/firmware/j7-main-r5f1_0-fw " \ "5 /lib/firmware/j7-main-r5f1_1-fw " \ @@ -144,9 +139,11 @@ "3 /lib/firmware/j7200-main-r5f0_1-fw " #endif /* CONFIG_TARGET_J7200_A72_EVM */ -/* set default dfu_bufsiz to 128KB (sector size of OSPI) */ +#ifndef EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY +#define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY +#endif + #define EXTRA_ENV_DFUARGS \ - "dfu_bufsiz=0x20000\0" \ DFU_ALT_INFO_MMC \ DFU_ALT_INFO_EMMC \ DFU_ALT_INFO_RAM \ @@ -160,6 +157,26 @@ #define EXTRA_ENV_J721E_BOARD_SETTINGS_MTD #endif +#if CONFIG_IS_ENABLED(CMD_PXE) +# define BOOT_TARGET_PXE(func) func(PXE, pxe, na) +#else +# define BOOT_TARGET_PXE(func) +#endif + +#if CONFIG_IS_ENABLED(CMD_DHCP) +# define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na) +#else +# define BOOT_TARGET_DHCP(func) +#endif + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ + BOOT_TARGET_PXE(func) \ + BOOT_TARGET_DHCP(func) + +#include + /* Incorporate settings into the U-Boot environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ @@ -170,7 +187,9 @@ EXTRA_ENV_RPROC_SETTINGS \ EXTRA_ENV_DFUARGS \ DEFAULT_UFS_TI_ARGS \ - EXTRA_ENV_J721E_BOARD_SETTINGS_MTD + EXTRA_ENV_J721E_BOARD_SETTINGS_MTD \ + EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY \ + BOOTENV /* Now for the remaining common defines */ #include