X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fiocon.h;h=9d9dabf24246553198b10ea336a1f89d75df82b5;hb=d126e016493dc84a87db4ce87db4c5a94ee29e9a;hp=5e61b11372a6bc98da033717549f6ea5cc32424e;hpb=0c0892be0d93a5a892b93739c5eb3bf692fed4ff;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/iocon.h b/include/configs/iocon.h
index 5e61b11..9d9dabf 100644
--- a/include/configs/iocon.h
+++ b/include/configs/iocon.h
@@ -2,30 +2,13 @@
  * (C) Copyright 2010
  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
 #define CONFIG_405EP		1	/* this is a PPC405 CPU */
-#define CONFIG_4xx		1	/*  member of PPC4xx family */
 #define CONFIG_IOCON		1	/*  on a IoCon board */
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
@@ -34,11 +17,13 @@
  * Include common defines/options for all AMCC eval boards
  */
 #define CONFIG_HOSTNAME		iocon
-#define CONFIG_IDENT_STRING	" iocon 0.03"
+#define CONFIG_IDENT_STRING	" iocon 0.06"
 #include "amcc-common.h"
 
-#define CONFIG_BOARD_EARLY_INIT_F	/* call board_early_init_f */
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
 #define CONFIG_LAST_STAGE_INIT
+#define CONFIG_SYS_GENERIC_BOARD
 
 #define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll   */
 
@@ -48,9 +33,12 @@
 #define PLLMR0_DEFAULT PLLMR0_266_133_66
 #define PLLMR1_DEFAULT PLLMR1_266_133_66
 
+#undef CONFIG_ZERO_BOOTDELAY_CHECK	/* ignore keypress on bootdelay==0 */
+
 /* new uImage format support */
 #define CONFIG_FIT
 #define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+#define CONFIG_FIT_DISABLE_SHA256
 
 #define CONFIG_ENV_IS_IN_FLASH	/* use FLASH for environment vars */
 
@@ -74,7 +62,12 @@
  * Commands additional to the ones defined in amcc-common.h
  */
 #define CONFIG_CMD_CACHE
+#define CONFIG_CMD_FPGAD
 #undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_ELF
+#undef CONFIG_CMD_I2C
+#undef CONFIG_CMD_IRQ
+#undef CONFIG_CMD_NFS
 
 /*
  * SDRAM configuration (please see cpu/ppc/sdram.[ch])
@@ -105,29 +98,76 @@
 /*
  * I2C stuff
  */
-#define CONFIG_SYS_I2C_SPEED		400000
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+#define CONFIG_SYS_I2C_IHS
 
-/* enable I2C and select the hardware/software driver */
-#undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
-#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
+#define CONFIG_SYS_I2C_SPEED		400000
+#define CONFIG_SYS_SPD_BUS_NUM		4
+
+#define CONFIG_PCA953X			/* NXP PCA9554 */
+#define CONFIG_PCA9698			/* NXP PCA9698 */
+
+#define CONFIG_SYS_I2C_IHS_CH0
+#define CONFIG_SYS_I2C_IHS_SPEED_0		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_0		0x7F
+#define CONFIG_SYS_I2C_IHS_CH1
+#define CONFIG_SYS_I2C_IHS_SPEED_1		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_1		0x7F
+#define CONFIG_SYS_I2C_IHS_CH2
+#define CONFIG_SYS_I2C_IHS_SPEED_2		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_2		0x7F
+#define CONFIG_SYS_I2C_IHS_CH3
+#define CONFIG_SYS_I2C_IHS_SPEED_3		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_3		0x7F
 
 /*
  * Software (bit-bang) I2C driver configuration
  */
+#define CONFIG_SYS_I2C_SOFT
+#define CONFIG_SYS_I2C_SOFT_SPEED		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE		0x7F
+#define I2C_SOFT_DECLARATIONS2
+#define CONFIG_SYS_I2C_SOFT_SPEED_2		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_2		0x7F
+#define I2C_SOFT_DECLARATIONS3
+#define CONFIG_SYS_I2C_SOFT_SPEED_3		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_3		0x7F
+#define I2C_SOFT_DECLARATIONS4
+#define CONFIG_SYS_I2C_SOFT_SPEED_4		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_4		0x7F
+
+#define CONFIG_SYS_ICS8N3QV01_I2C		{5, 6, 7, 8}
+#define CONFIG_SYS_CH7301_I2C			{5, 6, 7, 8}
+#define CONFIG_SYS_DP501_I2C			{0, 1, 2, 3}
 
 #ifndef __ASSEMBLY__
-void fpga_gpio_set(int pin);
-void fpga_gpio_clear(int pin);
-int fpga_gpio_get(int pin);
+void fpga_gpio_set(unsigned int bus, int pin);
+void fpga_gpio_clear(unsigned int bus, int pin);
+int fpga_gpio_get(unsigned int bus, int pin);
 #endif
 
 #define I2C_ACTIVE	{ }
 #define I2C_TRISTATE	{ }
-#define I2C_READ	fpga_gpio_get(0x0040) ? 1 : 0
-#define I2C_SDA(bit)	if (bit) fpga_gpio_set(0x0040); \
-			else fpga_gpio_clear(0x0040)
-#define I2C_SCL(bit)	if (bit) fpga_gpio_set(0x0020); \
-			else fpga_gpio_clear(0x0020)
+#define I2C_READ \
+	(fpga_gpio_get(I2C_ADAP_HWNR, 0x0040) ? 1 : 0)
+#define I2C_SDA(bit) \
+	do { \
+		if (bit) \
+			fpga_gpio_set(I2C_ADAP_HWNR, 0x0040); \
+		else \
+			fpga_gpio_clear(I2C_ADAP_HWNR, 0x0040); \
+	} while (0)
+#define I2C_SCL(bit) \
+	do { \
+		if (bit) \
+			fpga_gpio_set(I2C_ADAP_HWNR, 0x0020); \
+		else \
+			fpga_gpio_clear(I2C_ADAP_HWNR, 0x0020); \
+	} while (0)
 #define I2C_DELAY	udelay(25)	/* 1/4 I2C clock duration */
 
 /*
@@ -146,7 +186,6 @@ int fpga_gpio_get(int pin);
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write/ms */
 
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buff'd writes */
-#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware flash protect */
 
 #define CONFIG_SYS_FLASH_EMPTY_INFO	/* 'E' for empty sector on flinfo */
 #define CONFIG_SYS_FLASH_QUIET_TEST	1	/* no warn upon unknown flash */
@@ -214,9 +253,8 @@ int fpga_gpio_get(int pin);
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
 #define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128  /* size/bytes res'd for init data*/
 #define CONFIG_SYS_GBL_DATA_OFFSET \
-	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+	(CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
@@ -231,13 +269,20 @@ int fpga_gpio_get(int pin);
 #define CONFIG_SYS_EBC_PB1AP		0x92015480
 #define CONFIG_SYS_EBC_PB1CR		0xFB858000
 
-/* Memory Bank 2 (FPGA) initialization */
-#define CONFIG_SYS_FPGA_BASE		0x7f100000
+/* Memory Bank 2 (FPGA0) initialization */
+#define CONFIG_SYS_FPGA0_BASE		0x7f100000
 #define CONFIG_SYS_EBC_PB2AP		0x02825080
-#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_FPGA_BASE | 0x1a000)
+#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_FPGA0_BASE | 0x1a000)
+
+#define CONFIG_SYS_FPGA_BASE(k)		CONFIG_SYS_FPGA0_BASE
+#define CONFIG_SYS_FPGA_DONE(k)		0x0010
 
-#define CONFIG_SYS_FPGA_RFL_LOW		0x0000
-#define CONFIG_SYS_FPGA_RFL_HIGH	0x00fe
+#define CONFIG_SYS_FPGA_COUNT		1
+
+#define CONFIG_SYS_MCLINK_MAX		3
+
+#define CONFIG_SYS_FPGA_PTR \
+	{ (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
 
 /* Memory Bank 3 (Latches) initialization */
 #define CONFIG_SYS_LATCH_BASE		0x7f200000
@@ -249,4 +294,15 @@ int fpga_gpio_get(int pin);
 #define CONFIG_SYS_LATCH1_RESET		0xffff
 #define CONFIG_SYS_LATCH1_BOOT		0xffff
 
+/*
+ * OSD Setup
+ */
+#define CONFIG_SYS_MPC92469AC
+#define CONFIG_SYS_OSD_SCREENS		1
+#define CONFIG_SYS_DP501_DIFFERENTIAL
+#define CONFIG_SYS_DP501_VCAPCTRL0	0x01 /* DDR mode 0, DE for H/VSYNC */
+
+#define CONFIG_BITBANGMII		/* bit-bang MII PHY management */
+#define CONFIG_BITBANGMII_MULTI
+
 #endif	/* __CONFIG_H */