X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fio64.h;h=6915b2071c03652ea136cb2fd1cbf3ba01db0826;hb=247161b8160fc699b0a517f081220bb50bc502a8;hp=bb29bedb2d2a509ee0ce1b575538f2ba0c6ad388;hpb=880540decfb855e96bc14ac84ac7784669e4b382;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/io64.h b/include/configs/io64.h
index bb29bed..6915b20 100644
--- a/include/configs/io64.h
+++ b/include/configs/io64.h
@@ -6,23 +6,7 @@
  * by Stefan Roese, DENX Software Engineering, sr@denx.de.
  * and Grant Erickson <gerickson@nuovations.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 /************************************************************************
@@ -36,7 +20,6 @@
  * High Level Configuration Options
  *----------------------------------------------------------------------*/
 #define CONFIG_IO64		1		/* Board is Io64 */
-#define CONFIG_4xx		1		/* ... PPC4xx family */
 #define CONFIG_405EX		1		/* Specifc 405EX support*/
 #define CONFIG_SYS_CLK_FREQ	33333333	/* ext frequency to pll */
 
@@ -514,6 +497,12 @@
 
 #define CONFIG_SYS_FPGA_COUNT		2
 
+#define CONFIG_SYS_FPGA_PTR { \
+	(struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \
+	(struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE }
+
+#define CONFIG_SYS_FPGA_COMMON
+
 #define CONFIG_SYS_LATCH0_RESET		0xffff
 #define CONFIG_SYS_LATCH0_BOOT		0xffff
 #define CONFIG_SYS_LATCH1_RESET		0xffbf