X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fintip.h;h=ed96b1b3c44da058d386ec83b1b99cfdf94bed62;hb=842033e6964e9e5d34aca893c1845416dd8ac2cc;hp=4f7bc7e28dc8c2cd586223757bebbc6d22fb9d44;hpb=ecdd98799fab9174928f114778b8b261944b23b1;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/intip.h b/include/configs/intip.h
index 4f7bc7e..ed96b1b 100644
--- a/include/configs/intip.h
+++ b/include/configs/intip.h
@@ -37,14 +37,18 @@
 #define CONFIG_460EX		1	/* Specific PPC460EX		*/
 #ifdef CONFIG_DEVCONCENTER
 #define CONFIG_HOSTNAME		devconcenter
-#define CONFIG_IDENT_STRING	" devconcenter 0.02"
+#define CONFIG_IDENT_STRING	" devconcenter 0.06"
 #else
 #define CONFIG_HOSTNAME		intip
-#define CONFIG_IDENT_STRING	" intip 0.02"
+#define CONFIG_IDENT_STRING	" intip 0.06"
 #endif
 #define CONFIG_440		1
 #define CONFIG_4xx		1	/* ... PPC4xx family */
 
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xFFFA0000
+#endif
+
 /*
  * Include common defines/options for all AMCC eval boards
  */
@@ -59,6 +63,10 @@
 #define CONFIG_FIT
 #define CFG_ALT_MEMTEST
 
+#undef CONFIG_ZERO_BOOTDELAY_CHECK     /* ignore keypress on bootdelay==0 */
+#define CONFIG_AUTOBOOT_KEYED          /* use key strings to stop autoboot */
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
@@ -93,26 +101,24 @@
 
 #define CONFIG_SYS_OCM_BASE		0xE3000000	/* OCM: 64k */
 #define CONFIG_SYS_SRAM_BASE		0xE8000000	/* SRAM: 256k */
+#define CONFIG_SYS_SRAM_SIZE		(256 << 10)
 #define CONFIG_SYS_LOCAL_CONF_REGS	0xEF000000
 
-#define CONFIG_SYS_PERIPHERAL_BASE	0xEF600000	/* internal periph. */
-
 #define CONFIG_SYS_AHB_BASE		0xE2000000	/* int. AHB periph. */
 
 /*
  * Initial RAM & stack pointer (placed in OCM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM */
-#define CONFIG_SYS_INIT_RAM_END	(4 << 10)
-#define CONFIG_SYS_GBL_DATA_SIZE	256	/* num bytes initial data */
+#define CONFIG_SYS_INIT_RAM_SIZE	(4 << 10)
 #define CONFIG_SYS_GBL_DATA_OFFSET \
-	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
  * Serial Port
  */
-#undef CONFIG_UART1_CONSOLE	/* define this if you want console on UART1 */
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
 
 /*
  * Environment
@@ -172,7 +178,7 @@
 #define CONFIG_SYS_SDRAM_R3BAS		0x00000000
 #define CONFIG_SYS_SDRAM_PLBADDULL	0x00000000
 #define CONFIG_SYS_SDRAM_PLBADDUHB	0x00000008
-#define CONFIG_SYS_SDRAM_CONF1LL	0x80001C80
+#define CONFIG_SYS_SDRAM_CONF1LL	0x80001C00
 #define CONFIG_SYS_SDRAM_CONF1HB	0x80001C80
 #define CONFIG_SYS_SDRAM_CONFPATHB	0x10a68000
 
@@ -181,7 +187,7 @@
 #define CONFIG_SYS_SDRAM0_MB1CF		0x00000000
 #define CONFIG_SYS_SDRAM0_MB2CF		0x00000000
 #define CONFIG_SYS_SDRAM0_MB3CF		0x00000000
-#define CONFIG_SYS_SDRAM0_MCOPT1	0x05122000
+#define CONFIG_SYS_SDRAM0_MCOPT1	0x05120000
 #define CONFIG_SYS_SDRAM0_MCOPT2	0x00000000
 #define CONFIG_SYS_SDRAM0_MODT0		0x00000000
 #define CONFIG_SYS_SDRAM0_MODT1		0x00000000
@@ -193,29 +199,29 @@
 #define CONFIG_SYS_SDRAM0_INITPLR1	0x81900400
 #define CONFIG_SYS_SDRAM0_INITPLR2	0x81020000
 #define CONFIG_SYS_SDRAM0_INITPLR3	0x81030000
-#define CONFIG_SYS_SDRAM0_INITPLR4	0x81010000
-#define CONFIG_SYS_SDRAM0_INITPLR5	0xE4000542
+#define CONFIG_SYS_SDRAM0_INITPLR4	0x81010002
+#define CONFIG_SYS_SDRAM0_INITPLR5	0xE4000552
 #define CONFIG_SYS_SDRAM0_INITPLR6	0x81900400
 #define CONFIG_SYS_SDRAM0_INITPLR7	0x8A880000
 #define CONFIG_SYS_SDRAM0_INITPLR8	0x8A880000
 #define CONFIG_SYS_SDRAM0_INITPLR9	0x8A880000
 #define CONFIG_SYS_SDRAM0_INITPLR10	0x8A880000
-#define CONFIG_SYS_SDRAM0_INITPLR11	0x81000442
-#define CONFIG_SYS_SDRAM0_INITPLR12	0x81010380
-#define CONFIG_SYS_SDRAM0_INITPLR13	0x81010000
+#define CONFIG_SYS_SDRAM0_INITPLR11	0x81000452
+#define CONFIG_SYS_SDRAM0_INITPLR12	0x81010382
+#define CONFIG_SYS_SDRAM0_INITPLR13	0x81010002
 #define CONFIG_SYS_SDRAM0_INITPLR14	0x00000000
 #define CONFIG_SYS_SDRAM0_INITPLR15	0x00000000
 #define CONFIG_SYS_SDRAM0_RQDC		0x80000038
-#define CONFIG_SYS_SDRAM0_RFDC		0x003F0000
-#define CONFIG_SYS_SDRAM0_RDCC		0x80000000
+#define CONFIG_SYS_SDRAM0_RFDC		0x00000257
+#define CONFIG_SYS_SDRAM0_RDCC		0x40000000
 #define CONFIG_SYS_SDRAM0_DLCR		0x00000000
 #define CONFIG_SYS_SDRAM0_CLKTR		0x40000000
-#define CONFIG_SYS_SDRAM0_WRDTR		0x84000800
+#define CONFIG_SYS_SDRAM0_WRDTR		0x86000823
 #define CONFIG_SYS_SDRAM0_SDTR1		0x80201000
 #define CONFIG_SYS_SDRAM0_SDTR2		0x32204232
-#define CONFIG_SYS_SDRAM0_SDTR3		0x090B0D15
-#define CONFIG_SYS_SDRAM0_MMODE		0x00000442
-#define CONFIG_SYS_SDRAM0_MEMODE	0x00000000
+#define CONFIG_SYS_SDRAM0_SDTR3		0x090C0D15
+#define CONFIG_SYS_SDRAM0_MMODE		0x00000452
+#define CONFIG_SYS_SDRAM0_MEMODE	0x00000002
 
 #define CONFIG_SYS_MBYTES_SDRAM	256	/* 256MB */
 
@@ -310,6 +316,7 @@
  */
 /* General PCI */
 #define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
 #define CONFIG_PCI_PNP			/* do pci plug-and-play   */
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup  */
 #define CONFIG_PCI_CONFIG_HOST_BRIDGE