X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fintegrator-common.h;h=7a55c6aeefc61e3e85eb659c9a775e0d69687c8e;hb=4db386655a889b6466d2c3f40839ad21205c6d21;hp=b573bdc64f65a4d85ba8bd8e684799bff600e05b;hpb=e908d20fcbd847e17345591fc171b59d9a156516;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h
index b573bdc..7a55c6a 100644
--- a/include/configs/integrator-common.h
+++ b/include/configs/integrator-common.h
@@ -6,34 +6,7 @@
  * Common ARM Integrator configuration settings
  */
 
-#define CONFIG_SYS_TIMERBASE		0x13000100	/* Timer1 */
-
-/*
- * There are various dependencies on the core module (CM) fitted
- * Users should refer to their CM user guide
- */
-#include "armcoremodule.h"
-
-/*
- * Initialize and remap the core module, use SPD to detect memory size
- * If CONFIG_SKIP_LOWLEVEL_INIT is not defined &
- * the core module has a CM_INIT register
- * then the U-Boot initialisation code will
- * e.g. ARM Boot Monitor or pre-loader is repeated once
- * (to re-initialise any existing CM_INIT settings to safe values).
- *
- * This is usually not the desired behaviour since the platform
- * will either reboot into the ARM monitor (or pre-loader)
- * or continuously cycle thru it without U-Boot running,
- * depending upon the setting of Integrator/CP switch S2-4.
- *
- * However it may be needed if Integrator/CP switch S2-1
- * is set OFF to boot direct into U-Boot.
- * In that case comment out the line below.
- */
-#define CONFIG_CM_INIT
-#define CONFIG_CM_REMAP
-#define CONFIG_CM_SPD_DETECT
+#define CFG_SYS_TIMERBASE		0x13000100	/* Timer1 */
 
 /*
  * The ARM boot monitor initializes the board.
@@ -57,12 +30,7 @@
  */
 #define PHYS_SDRAM_1		0x00000000	/* SDRAM Bank #1 */
 #define PHYS_SDRAM_1_SIZE	0x08000000	/* 128 MB */
-#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_SIZE PHYS_SDRAM_1_SIZE
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \
-				    CONFIG_SYS_INIT_RAM_SIZE - \
-				    GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET
+#define CFG_SYS_SDRAM_BASE	PHYS_SDRAM_1
 
 /*
  * FLASH and environment organization
@@ -73,10 +41,6 @@
  * - SIB block
  * - U-Boot environment
  */
-#define CONFIG_SYS_FLASH_BASE		0x24000000
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CFG_SYS_FLASH_BASE		0x24000000
 
 /* Timeout values in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	(2 * CONFIG_SYS_HZ) /* Erase Timeout */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	(2 * CONFIG_SYS_HZ) /* Write Timeout */
-#define CONFIG_SYS_FLASH_EMPTY_INFO	/* flinfo indicates empty blocks */