X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Finnokom.h;h=a0a3da1e82c0d00762e58ec9762e1632b7ea4e5d;hb=10d1a160f5e28b05f891c050ca2f23855b226f5f;hp=709c0d7a9934e7bf68342b82fa304441f08ddac8;hpb=a8c7c708a9e0051c6358718c53572a4681eaa22b;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/innokom.h b/include/configs/innokom.h index 709c0d7..a0a3da1 100644 --- a/include/configs/innokom.h +++ b/include/configs/innokom.h @@ -31,20 +31,20 @@ #define __CONFIG_H /* - * If we are developing, we might want to start U-Boot from ram - * so we MUST NOT initialize critical regs like mem-timing ... - */ -#define CONFIG_INIT_CRITICAL /* undef for developing */ - -/* * High Level Configuration Options * (easy to change) */ -#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ +#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ #define CONFIG_INNOKOM 1 /* on an Auerswald Innokom board */ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ /* for timer/console/ethernet */ + +#define CONFIG_SYS_TEXT_BASE 0x0 + +/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_DCACHE_OFF + /* * Hardware drivers */ @@ -52,6 +52,7 @@ /* * select serial console configuration */ +#define CONFIG_PXA_SERIAL #define CONFIG_FFUART 1 /* we use FFUART on CSB226 */ /* allow to overwrite serial and ethaddr */ @@ -60,10 +61,34 @@ #define CONFIG_BAUDRATE 19200 #define CONFIG_MISC_INIT_R 1 /* we have a misc_init_r() function */ -#define CONFIG_COMMANDS (CFG_CMD_BDI|CFG_CMD_LOADB|CFG_CMD_IMI|CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_NET|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO|CFG_CMD_I2C|CFG_CMD_DHCP|CFG_CMD_CACHE) -/* CONFIG_CMD_DFL|CFG_CMD_I2C|CFG_CMD_EEPROM|CFG_CMD_NET|CFG_CMD_JFFS2|CFG_CMD_DHCP) */ -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BDI +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IMI +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_NET +#define CONFIG_CMD_RUN + #define CONFIG_BOOTDELAY 3 /* #define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200" */ @@ -82,66 +107,64 @@ */ /* - * Size of malloc() pool; this lives below the uppermost 128 KiB which are - * used for the RAM copy of the uboot code - * + * Size of malloc() pool */ -#define CFG_MALLOC_LEN (256*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "uboot> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_MALLOC_LEN (256*1024) -#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ +#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ -#define CFG_LOAD_ADDR 0xa3000000 /* load kernel to this address */ +#define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* load kernel to this address */ -#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CONFIG_SYS_HZ 1000 /* RS: the oscillator is actually 3680130?? */ -#define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */ +#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */ /* 0101000001 */ /* ^^^^^ Memory Speed 99.53 MHz */ /* ^^ Run Mode Speed = 2x Mem Speed */ /* ^^ Turbo Mode Sp. = 1x Run M. Sp. */ -#define CFG_MONITOR_LEN 0x20000 /* 128 KiB */ +#define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128 KiB */ /* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* * I2C bus */ -#define CONFIG_HARD_I2C 1 -#define CFG_I2C_SPEED 50000 -#define CFG_I2C_SLAVE 0xfe - -#define CFG_ENV_IS_IN_EEPROM 1 - -#define CFG_ENV_OFFSET 0x00 /* environment starts here */ -#define CFG_ENV_SIZE 1024 /* 1 KiB */ -#define CFG_I2C_EEPROM_ADDR 0x50 /* A0 = 0 (hardwired) */ -#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 15 /* between stop and start */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 /* length of address */ -#define CFG_EEPROM_SIZE 4096 /* size in bytes */ -#define CFG_I2C_INIT_BOARD 1 /* board has it's own init */ +#define CONFIG_I2C_MV 1 +#define CONFIG_MV_I2C_REG 0x40301680 +#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C_SPEED 50000 +#define CONFIG_SYS_I2C_SLAVE 0xfe + +#define CONFIG_ENV_IS_IN_EEPROM 1 + +#define CONFIG_ENV_OFFSET 0x00 /* environment starts here */ +#define CONFIG_ENV_SIZE 1024 /* 1 KiB */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* A0 = 0 (hardwired) */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15 /* between stop and start */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* length of address */ +#define CONFIG_SYS_EEPROM_SIZE 4096 /* size in bytes */ +#define CONFIG_SYS_I2C_INIT_BOARD 1 /* board has it's own init */ /* * SMSC91C111 Network Card */ -#define CONFIG_DRIVER_SMC91111 1 +#define CONFIG_SMC91111 1 #define CONFIG_SMC91111_BASE 0x14000000 /* chip select 5 */ #undef CONFIG_SMC_USE_32_BIT /* 16 bit bus access */ #undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */ +#define CONFIG_SMC_AUTONEG_TIMEOUT 10 /* timeout 10 seconds */ #undef CONFIG_SHOW_ACTIVITY #define CONFIG_NET_RETRY_COUNT 10 /* # of retries */ @@ -166,19 +189,50 @@ #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ #define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */ -#define CFG_DRAM_BASE 0xa0000000 /* RAM starts here */ -#define CFG_DRAM_SIZE 0x04000000 +#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* RAM starts here */ +#define CONFIG_SYS_DRAM_SIZE 0x04000000 -#define CFG_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1) /* - * JFFS2 Partitions + * JFFS2 partitions + * */ -#define CFG_JFFS_CUSTOM_PART 1 /* see board/innokom/flash.c */ -#define CONFIG_MTD_INNOKOM_16MB 1 /* development flash */ -#undef CONFIG_MTD_INNOKOM_64MB /* production flash */ +/* development flash */ +#define CONFIG_MTD_INNOKOM_16MB 1 +#undef CONFIG_MTD_INNOKOM_64MB +/* production flash */ +/* +#define CONFIG_MTD_INNOKOM_64MB 1 +#undef CONFIG_MTD_INNOKOM_16MB +*/ + +/* No command line, one static partition, whole device */ +#undef CONFIG_CMD_MTDPARTS +#define CONFIG_JFFS2_DEV "nor0" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support */ +/* Note: fake mtd_id used, no linux mtd map file */ +/* +#define CONFIG_CMD_MTDPARTS +#define MTDIDS_DEFAULT "nor0=innokom-0" +*/ + +/* development flash */ +/* +#define MTDPARTS_DEFAULT "mtdparts=innokom-0:256k(uboot),768k(kernel),8m(user),7m(data)" +*/ + +/* production flash */ +/* +#define MTDPARTS_DEFAULT "mtdparts=innokom-0:256k(uboot),768k(kernel),16256k(user1),16256k(user2),32m(data)" +*/ /* * GPIO settings @@ -197,9 +251,9 @@ * GP79 == nCS3 is 1 * GP80 == nCS4 is 1 */ -#define CFG_GPSR0_VAL 0x03008000 -#define CFG_GPSR1_VAL 0xC0028282 -#define CFG_GPSR2_VAL 0x0001C000 +#define CONFIG_SYS_GPSR0_VAL 0x03008000 +#define CONFIG_SYS_GPSR1_VAL 0xC0028282 +#define CONFIG_SYS_GPSR2_VAL 0x0001C000 /* GP02 == DON_RST is 0 * GP23 == SCLK is 0 @@ -208,9 +262,9 @@ * GP61 == LED_A is 0 * GP73 == SWUPD_LED is 0 */ -#define CFG_GPCR0_VAL 0x00800004 -#define CFG_GPCR1_VAL 0x30002000 -#define CFG_GPCR2_VAL 0x00000100 +#define CONFIG_SYS_GPCR0_VAL 0x00800004 +#define CONFIG_SYS_GPCR1_VAL 0x30002000 +#define CONFIG_SYS_GPCR2_VAL 0x00000100 /* GP00 == DON_READY is input * GP01 == DON_OK is input @@ -255,9 +309,9 @@ * GP79 == nCS3 is output * GP80 == nCS4 is output */ -#define CFG_GPDR0_VAL 0x03808004 -#define CFG_GPDR1_VAL 0xF002A282 -#define CFG_GPDR2_VAL 0x0001C200 +#define CONFIG_SYS_GPDR0_VAL 0x03808004 +#define CONFIG_SYS_GPDR1_VAL 0xF002A282 +#define CONFIG_SYS_GPDR2_VAL 0x0001C200 /* GP15 == nCS1 is AF10 * GP18 == RDY is AF01 @@ -277,12 +331,12 @@ * GP79 == nCS3 is AF10 * GP80 == nCS4 is AF10 */ -#define CFG_GAFR0_L_VAL 0x80000000 -#define CFG_GAFR0_U_VAL 0x001A8010 -#define CFG_GAFR1_L_VAL 0x60088058 -#define CFG_GAFR1_U_VAL 0x00000008 -#define CFG_GAFR2_L_VAL 0xA0000000 -#define CFG_GAFR2_U_VAL 0x00000002 +#define CONFIG_SYS_GAFR0_L_VAL 0x80000000 +#define CONFIG_SYS_GAFR0_U_VAL 0x001A8010 +#define CONFIG_SYS_GAFR1_L_VAL 0x60088058 +#define CONFIG_SYS_GAFR1_U_VAL 0x00000008 +#define CONFIG_SYS_GAFR2_L_VAL 0xA0000000 +#define CONFIG_SYS_GAFR2_U_VAL 0x00000002 /* FIXME: set GPIO_RER/FER */ @@ -293,7 +347,10 @@ * BFS = 1 * SSS = 1 */ -#define CFG_PSSR_VAL 0x37 +#define CONFIG_SYS_PSSR_VAL 0x37 + +#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10 +#define CONFIG_SYS_CKEN 0x0 /* * Memory settings @@ -314,7 +371,7 @@ * [03] 1 - 16 Bit bus width * [02:00] 000 - nonburst RAM or FLASH */ -#define CFG_MSC0_VAL 0x25b825b8 /* flash banks */ +#define CONFIG_SYS_MSC0_VAL 0x25b825b8 /* flash banks */ /* This is the configuration for nCS2/3 -> TDM-Switch, DSP * configuration for nCS3: DSP @@ -332,7 +389,7 @@ * [03] 1 - 16 Bit bus width * [02:00] 100 - variable latency I/O */ -#define CFG_MSC1_VAL 0x123C593C /* TDM switch, DSP */ +#define CONFIG_SYS_MSC1_VAL 0x123C593C /* TDM switch, DSP */ /* This is the configuration for nCS4/5 -> ExtBus, LAN Controller * @@ -351,7 +408,7 @@ * [03] 1 - 16 Bit bus width * [02:00] 100 - variable latency I/O */ -#define CFG_MSC2_VAL 0x123C6CDC /* extra bus, LAN controller */ +#define CONFIG_SYS_MSC2_VAL 0x123C6CDC /* extra bus, LAN controller */ /* MDCNFG: SDRAM Configuration Register * @@ -379,7 +436,7 @@ * [00] 1 - enable SDRAM partition 0 */ /* use the configuration above but disable partition 0 */ -#define CFG_MDCNFG_VAL 0x000019c8 +#define CONFIG_SYS_MDCNFG_VAL 0x000019c8 /* MDREFR: SDRAM Refresh Control Register * @@ -400,7 +457,7 @@ * [12] 1 - E0PIN: disable SDCKE0 * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24 */ -#define CFG_MDREFR_VAL 0x0081D018 +#define CONFIG_SYS_MDREFR_VAL 0x0081D018 /* MDMRS: Mode Register Set Configuration Register * @@ -415,18 +472,21 @@ * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential. * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4. */ -#define CFG_MDMRS_VAL 0x00020022 +#define CONFIG_SYS_MDMRS_VAL 0x00020022 /* * PCMCIA and CF Interfaces */ -#define CFG_MECR_VAL 0x00000000 -#define CFG_MCMEM0_VAL 0x00000000 -#define CFG_MCMEM1_VAL 0x00000000 -#define CFG_MCATT0_VAL 0x00000000 -#define CFG_MCATT1_VAL 0x00000000 -#define CFG_MCIO0_VAL 0x00000000 -#define CFG_MCIO1_VAL 0x00000000 +#define CONFIG_SYS_MECR_VAL 0x00000000 +#define CONFIG_SYS_MCMEM0_VAL 0x00000000 +#define CONFIG_SYS_MCMEM1_VAL 0x00000000 +#define CONFIG_SYS_MCATT0_VAL 0x00000000 +#define CONFIG_SYS_MCATT1_VAL 0x00000000 +#define CONFIG_SYS_MCIO0_VAL 0x00000000 +#define CONFIG_SYS_MCIO1_VAL 0x00000000 + +#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 +#define CONFIG_SYS_SXCNFG_VAL 0x00000000 /* #define CSB226_USER_LED0 0x00000008 @@ -437,11 +497,11 @@ /* * FLASH and environment organization */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sect. on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sect. on one chip */ /* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ +#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */ #endif /* __CONFIG_H */