X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fimx8mq_phanbell.h;h=1905e538c5befe1f1fac99dbb44e6fe51c036fde;hb=6cc04547cb3bbd3a3d78947f200acbae19e3c67f;hp=f6410114b765b656381462ca26765d626aa23cb9;hpb=adfaa4284c0941161baa191b35e3a866c6d5ef4d;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h index f641011..1905e53 100644 --- a/include/configs/imx8mq_phanbell.h +++ b/include/configs/imx8mq_phanbell.h @@ -9,29 +9,19 @@ #include #include -#define CONFIG_SPL_MAX_SIZE (172 * 1024) -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) - #ifdef CONFIG_SPL_BUILD /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ -#define CONFIG_SPL_STACK 0x187FF0 -#define CONFIG_SPL_BSS_START_ADDR 0x00180000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x182000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif /* ENET Config */ /* ENET1 */ #if defined(CONFIG_CMD_NET) #define CONFIG_FEC_MXC_PHYADDR 0 -#define FEC_QUIRK_ENET_MAC #endif #define CONFIG_MFG_ENV_SETTINGS \ @@ -96,26 +86,15 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */ -#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1) -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_USDHC_NUM 2 +#define CFG_SYS_FSL_ESDHC_ADDR 0 #endif