X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fimx8mq_evk.h;h=ecf4c2e46b7ba61b7c1428288a22d8c441fc0670;hb=04da42770b0cc3bea8841972bfc9568299ece826;hp=7759bbf2645f7d05ae303c91b409d9bcdbcd00a2;hpb=8b1d3d19be6918ed4488fb1157deabc6c6c42481;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index 7759bbf..ecf4c2e 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -9,10 +9,6 @@ #include #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CSF_SIZE 0x2000 /* 8K region */ -#endif - #define CONFIG_SPL_MAX_SIZE (124 * 1024) #define CONFIG_SYS_MONITOR_LEN (512 * 1024) #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR @@ -36,8 +32,6 @@ #define CONFIG_SYS_SPL_MALLOC_START 0x42200000 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 -#define CONFIG_SYS_ICACHE_OFF -#define CONFIG_SYS_DCACHE_OFF /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x182000 @@ -71,7 +65,6 @@ #undef CONFIG_CMD_IMLS #undef CONFIG_CMD_CRC32 -#undef CONFIG_BOOTM_NETBSD /* ENET Config */ /* ENET1 */ @@ -89,9 +82,6 @@ #define CONFIG_PHY_GIGE #define IMX_FEC_BASE 0x30BE0000 - -#define CONFIG_PHYLIB -#define CONFIG_PHY_ATHEROS #endif #define CONFIG_MFG_ENV_SETTINGS \ @@ -110,11 +100,11 @@ CONFIG_MFG_ENV_SETTINGS \ "script=boot.scr\0" \ "image=Image\0" \ - "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200\0" \ + "console=ttymxc0,115200\0" \ "fdt_addr=0x43000000\0" \ "fdt_high=0xffffffffffffffff\0" \ "boot_fdt=try\0" \ - "fdt_file=fsl-imx8mq-evk.dtb\0" \ + "fdt_file=imx8mq-evk.dtb\0" \ "initrd_addr=0x43800000\0" \ "initrd_high=0xffffffffffffffff\0" \ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ @@ -184,8 +174,6 @@ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_ENV_OVERWRITE -#define CONFIG_ENV_OFFSET (64 * SZ_64K) -#define CONFIG_ENV_SIZE 0x1000 #define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ @@ -218,8 +206,6 @@ #define CONFIG_IMX_BOOTAUX #define CONFIG_CMD_MMC -#define CONFIG_FSL_ESDHC -#define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0