X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fimx8mq_cm.h;h=6aad04e9e97e8c366fc229ee9fc20f6d2ee47731;hb=08574ed339fb474e7d984a2e48160615286e4515;hp=6eecfc813a4337433410731e9b3a73e536e20c6f;hpb=004d30c786056d443d40428c4b1c11e2f8f0bc32;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/imx8mq_cm.h b/include/configs/imx8mq_cm.h index 6eecfc8..6aad04e 100644 --- a/include/configs/imx8mq_cm.h +++ b/include/configs/imx8mq_cm.h @@ -10,37 +10,24 @@ #include #include -#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) - -#define CONFIG_SPL_MAX_SIZE (124 * 1024) -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) - #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x187FF0 -#define CONFIG_SPL_BSS_START_ADDR 0x00180000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x182000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif /* ENET Config */ /* ENET1 */ -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(MMC, mmc, 1) \ func(DHCP, dhcp, na) #include -#endif /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -61,10 +48,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE 0x40000000 @@ -73,13 +56,6 @@ #define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1) -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0