X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fimx8mp_rsb3720.h;h=5be46090a145dafc753b81658c639dafa7e8e7ec;hb=6cc04547cb3bbd3a3d78947f200acbae19e3c67f;hp=c5dd545471e17830e1599affc25cf0e6f81c8301;hpb=6e2af641e4bfed24d3edd8519dd40ec397361b4e;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h
index c5dd545..5be4609 100644
--- a/include/configs/imx8mp_rsb3720.h
+++ b/include/configs/imx8mp_rsb3720.h
@@ -12,10 +12,6 @@
 #include <asm/arch/imx-regs.h>
 #include <config_distro_bootcmd.h>
 
-#define CONFIG_SYS_BOOTM_LEN		(32 * SZ_1M)
-
-#define CONFIG_SPL_MAX_SIZE		(152 * 1024)
-#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
 #define CONFIG_SYS_UBOOT_BASE	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
 
 /* GUIDs for capsule updatable firmware images */
@@ -28,18 +24,11 @@
 		 0x5f, 0xd3, 0x6b, 0x9b, 0xe5, 0xb9)
 
 #ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_STACK		0x960000
-#define CONFIG_SPL_BSS_START_ADDR	0x0098FC00
-#define CONFIG_SPL_BSS_MAX_SIZE		0x400	/* 1 KB */
-#define CONFIG_SYS_SPL_MALLOC_START	0x42200000
-#define CONFIG_SYS_SPL_MALLOC_SIZE	SZ_512K	/* 512 KB */
-
 #define CONFIG_MALLOC_F_ADDR		0x184000 /* malloc f used before \
 						  * GD_FLG_FULL_MALLOC_INIT \
 						  * set \
 						  */
 
-#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
 
 #if defined(CONFIG_NAND_BOOT)
 #define CONFIG_SPL_NAND_MXS
@@ -51,12 +40,6 @@
 /* ENET1 */
 #if defined(CONFIG_CMD_NET)
 #define CONFIG_FEC_MXC_PHYADDR          4
-#define FEC_QUIRK_ENET_MAC
-
-#define DWC_NET_PHYADDR			4
-#ifdef CONFIG_DWC_ETH_QOS
-#define CONFIG_SYS_NONCACHED_MEMORY     (1 * SZ_1M)     /* 1M */
-#endif
 
 #define PHY_ANEG_TIMEOUT 20000
 
@@ -150,10 +133,6 @@
 /* Link Definitions */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
 #define CONFIG_SYS_INIT_RAM_SIZE	0x80000
-#define CONFIG_SYS_INIT_SP_OFFSET \
-	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
-	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 
 
 /* Totally 6GB or 4G DDR */
@@ -171,15 +150,8 @@
 
 #define CONFIG_MXC_UART_BASE		UART3_BASE_ADDR
 
-/* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE		2048
-#define CONFIG_SYS_MAXARGS		64
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
-					sizeof(CONFIG_SYS_PROMPT) + 16)
-
-#define CONFIG_SYS_FSL_USDHC_NUM	2
-#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CFG_SYS_FSL_USDHC_NUM	2
+#define CFG_SYS_FSL_ESDHC_ADDR	0
 
 #ifdef CONFIG_FSL_FSPI
 #define FSL_FSPI_FLASH_SIZE		SZ_32M
@@ -194,7 +166,6 @@
 #ifdef CONFIG_NAND_MXS
 
 /* NAND stuff */
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE           0x20000000
 #endif /* CONFIG_NAND_MXS */