X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fimx8mm_icore_mx8mm.h;h=9cdba70493b229d53691b60993a27313bf6c9ece;hb=6cc04547cb3bbd3a3d78947f200acbae19e3c67f;hp=d0aab994203abda992e47f50f1661d7eda1e0dcc;hpb=9b5f9aeb3b48dbc059272168635a397ea5096a31;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/imx8mm_icore_mx8mm.h b/include/configs/imx8mm_icore_mx8mm.h
index d0aab99..9cdba70 100644
--- a/include/configs/imx8mm_icore_mx8mm.h
+++ b/include/configs/imx8mm_icore_mx8mm.h
@@ -10,30 +10,19 @@
 #include <linux/sizes.h>
 #include <asm/arch/imx-regs.h>
 
-#define CONFIG_SYS_MONITOR_LEN		SZ_512K
 #define CONFIG_SYS_UBOOT_BASE \
 	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
 
 #ifdef CONFIG_SPL_BUILD
-# define CONFIG_SPL_STACK		0x920000
-# define CONFIG_SPL_BSS_START_ADDR	0x910000
-# define CONFIG_SYS_SPL_MALLOC_START	0x42200000
-# define CONFIG_SYS_SPL_MALLOC_SIZE	SZ_512K
-
 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
 # define CONFIG_MALLOC_F_ADDR		0x930000
 /* For RAW image gives a error info not panic */
-# define CONFIG_SPL_ABORT_ON_RAW_IMAGE
 #endif /* CONFIG_SPL_BUILD */
 
-#ifndef CONFIG_SPL_BUILD
 #define BOOT_TARGET_DEVICES(func) \
 	func(MMC, mmc, 2) \
 	func(MMC, mmc, 0)
 #include <config_distro_bootcmd.h>
-#else
-#define BOOTENV
-#endif
 
 #define ENV_MEM_LAYOUT_SETTINGS \
 	"fdt_addr_r=0x44000000\0" \
@@ -51,23 +40,15 @@
 
 #define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
 #define CONFIG_SYS_INIT_RAM_SIZE        SZ_2M
-#define CONFIG_SYS_INIT_SP_OFFSET \
-	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
-	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 
 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 
 /* SDRAM configuration */
 #define PHYS_SDRAM                      0x40000000
 #define PHYS_SDRAM_SIZE			SZ_2G /* 2GB DDR */
-#define CONFIG_SYS_BOOTM_LEN		SZ_256M
-
-/* UART */
-#define CONFIG_MXC_UART_BASE		UART_BASE_ADDR(2)
 
 /* USDHC */
-#define CONFIG_SYS_FSL_USDHC_NUM	2
-#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CFG_SYS_FSL_USDHC_NUM	2
+#define CFG_SYS_FSL_ESDHC_ADDR	0
 
 #endif /* __IMX8MM_ICORE_MX8MM_H */