X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fimx6_spl.h;h=a223930240c831e87d6fdd213038f88e57824c8c;hb=e4b91f085d4259f187052ff724c80af38fc11b18;hp=bda9541af6625e3c6460e8edbd0a03469c0a9ab6;hpb=267c5b79899dcbdfa190b8c6633a2bf517a73123;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h
index bda9541..a223930 100644
--- a/include/configs/imx6_spl.h
+++ b/include/configs/imx6_spl.h
@@ -1,20 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright (C) 2014 Gateworks Corporation
  * Author: Tim Harvey <tharvey@gateworks.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
  */
 #ifndef __IMX6_SPL_CONFIG_H
 #define __IMX6_SPL_CONFIG_H
 
 #ifdef CONFIG_SPL
 
-#define CONFIG_SPL_FRAMEWORK
-
+#ifdef CONFIG_MX6_OCRAM_256KB
 /*
- * see Figure 8-3 in IMX6DQ/IMX6SDL Reference manuals:
+ * see Figure 8.4.1 in IMX6DQ Reference manuals:
+ *  - IMX6DQ OCRAM (IRAM) is from 0x00907000 to 0x0093FFFF
+ *  - BOOT ROM stack is at 0x0093FFB8
+ *  - if icache/dcache is enabled (eFuse/strapping controlled) then the
+ *    IMX BOOT ROM will setup MMU table at 0x00938000, therefore we need to
+ *    fit between 0x00907000 and 0x00938000.
+ *  - Additionally the BOOT ROM loads what they consider the firmware image
+ *    which consists of a 4K header in front of us that contains the IVT, DCD
+ *    and some padding thus 'our' max size is really 0x00908000 - 0x00938000
+ *    or 192KB
+ */
+#define CONFIG_SPL_MAX_SIZE		0x30000
+#define CONFIG_SPL_STACK		0x0093FFB8
+/*
+ * Pad SPL to 196KB (4KB header + 192KB max size). This allows to write the
+ * SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a
+ * boot media (given that boot media specific offset is configured properly).
+ */
+#define CONFIG_SPL_PAD_TO		0x31000
+#else
+/*
+ * see Figure 8-3 in IMX6SDL Reference manuals:
  *  - IMX6SDL OCRAM (IRAM) is from 0x00907000 to 0x0091FFFF
- *  - IMX6DQ has 2x IRAM of IMX6SDL but we intend to support IMX6SDL as well
  *  - BOOT ROM stack is at 0x0091FFB8
  *  - if icache/dcache is enabled (eFuse/strapping controlled) then the
  *    IMX BOOT ROM will setup MMU table at 0x00918000, therefore we need to
@@ -24,8 +42,6 @@
  *    and some padding thus 'our' max size is really 0x00908000 - 0x00918000
  *    or 64KB
  */
-#define CONFIG_SPL_LDSCRIPT	"arch/arm/mach-omap2/u-boot-spl.lds"
-#define CONFIG_SPL_TEXT_BASE		0x00908000
 #define CONFIG_SPL_MAX_SIZE		0x10000
 #define CONFIG_SPL_STACK		0x0091FFB8
 /*
@@ -35,6 +51,8 @@
  */
 #define CONFIG_SPL_PAD_TO		0x11000
 
+#endif
+
 /* MMC support */
 #if defined(CONFIG_SPL_MMC_SUPPORT)
 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
@@ -48,22 +66,25 @@
 #endif
 
 /* Define the payload for FAT/EXT support */
-#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
-#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME  "u-boot.img"
+#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
+# ifdef CONFIG_OF_CONTROL
+#  define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot-dtb.img"
+# else
+#  define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
+# endif
 #endif
 
-#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6SL)
+#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6SL) || \
+	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
 #define CONFIG_SPL_BSS_START_ADDR      0x88200000
 #define CONFIG_SPL_BSS_MAX_SIZE        0x100000		/* 1 MB */
 #define CONFIG_SYS_SPL_MALLOC_START    0x88300000
 #define CONFIG_SYS_SPL_MALLOC_SIZE     0x100000		/* 1 MB */
-#define CONFIG_SYS_TEXT_BASE           0x87800000
 #else
 #define CONFIG_SPL_BSS_START_ADDR	0x18200000
 #define CONFIG_SPL_BSS_MAX_SIZE		0x100000	/* 1 MB */
 #define CONFIG_SYS_SPL_MALLOC_START	0x18300000
 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000	/* 1 MB */
-#define CONFIG_SYS_TEXT_BASE		0x17800000
 #endif
 #endif