X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fimx31_phycore.h;h=cb42a7cc96bbadbeea7055e8b8c19be3dbb30d7f;hb=47d19da4d3f9ac4787abe9dee32406478424be52;hp=7e9bfb504e7cb73214767b03b2f3f8a270dc2c22;hpb=3e0f331c05d72f140715c1e9fca991927e44d422;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h index 7e9bfb5..cb42a7c 100644 --- a/include/configs/imx31_phycore.h +++ b/include/configs/imx31_phycore.h @@ -4,7 +4,7 @@ * Richard Woodruff * Kshitij Gupta * - * Configuration settings for the 242x TI H4 board. + * Configuration settings for the phyCORE-i.MX31 board. * * See file CREDITS for list of people who contributed to this * project. @@ -51,8 +51,8 @@ /* * Size of malloc() pool */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128 * 1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ /* * Hardware drivers @@ -60,18 +60,18 @@ #define CONFIG_HARD_I2C 1 #define CONFIG_I2C_MXC 1 -#define CFG_I2C_MX31_PORT2 1 -#define CFG_I2C_SPEED 100000 -#define CFG_I2C_SLAVE 0xfe +#define CONFIG_SYS_I2C_MX31_PORT2 1 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0xfe -#define CONFIG_MX31_UART 1 -#define CFG_MX31_UART1 1 +#define CONFIG_MXC_UART 1 +#define CONFIG_SYS_MX31_UART1 1 /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 #define CONFIG_BAUDRATE 115200 -#define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} /*********************************************************** * Command definition @@ -113,20 +113,20 @@ /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "uboot> " -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "uboot> " +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_MEMTEST_START 0 /* memtest works on */ -#define CFG_MEMTEST_END 0x10000 +#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x10000 -#define CFG_LOAD_ADDR 0 /* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0 /* default load address */ -#define CFG_HZ 32000 +#define CONFIG_SYS_HZ 1000 #define CONFIG_CMDLINE_EDITING 1 @@ -147,35 +147,58 @@ /*----------------------------------------------------------------------- * FLASH and environment organization */ -#define CFG_FLASH_BASE 0xa0000000 -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 259 /* max number of sectors on one chip */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */ - -#define CFG_ENV_IS_IN_EEPROM 1 -#define CFG_ENV_OFFSET 0x00 /* environment starts here */ -#define CFG_ENV_SIZE 4096 -#define CFG_I2C_EEPROM_ADDR 0x52 -#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* between stop and start */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 /* length of byte address */ +#define CONFIG_SYS_FLASH_BASE 0xa0000000 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 259 /* max number of sectors on one chip */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ + +#define CONFIG_ENV_IS_IN_EEPROM 1 +#define CONFIG_ENV_OFFSET 0x00 /* environment starts here */ +#define CONFIG_ENV_SIZE 4096 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* between stop and start */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* length of byte address */ /*----------------------------------------------------------------------- * CFI FLASH driver setup */ -#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ -#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ +#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ +#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ /* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (100*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (100*CFG_HZ) /* Timeout for Flash Write */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ +#define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Write */ /* * JFFS2 partitions */ -#undef CONFIG_JFFS2_CMDLINE +#undef CONFIG_CMD_MTDPARTS #define CONFIG_JFFS2_DEV "nor0" +/* EET platform additions */ +#ifdef CONFIG_IMX31_PHYCORE_EET +#define BOARD_LATE_INIT + +#define CONFIG_MX31_GPIO 1 + +#define CONFIG_HARD_SPI 1 +#define CONFIG_MXC_SPI 1 +#define CONFIG_CMD_SPI + +#define CONFIG_S6E63D6 1 + +#define CONFIG_LCD 1 +#define CONFIG_VIDEO_MX3 1 +#define CONFIG_SYS_WHITE_ON_BLACK 1 +#define LCD_BPP LCD_COLOR8 +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 + +#define CONFIG_SPLASH_SCREEN 1 +#define CONFIG_CMD_BMP 1 +#endif + #endif /* __CONFIG_H */