X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fids8313.h;h=bcd8aee7c323ce62a3e8fea274f39ec4a55c8cc7;hb=35bd70c5107f0cfa610b5c7074a7ee2a60d5d82f;hp=7e4c497fe0ae65b22dd5a3f02d61c1593cccdf63;hpb=d94604d558cda9f89722c967d6f8d6269a2db21c;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 7e4c497..bcd8aee 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -11,59 +11,20 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include + /* * High Level Configuration Options */ -#define CONFIG_MPC831x -#define CONFIG_MPC8313 - -#define CONFIG_FSL_ELBC - #define CONFIG_BOOT_RETRY_TIME 900 #define CONFIG_BOOT_RETRY_MIN 30 #define CONFIG_RESET_TO_RETRY -#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ -#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN - -#define CONFIG_SYS_IMMR 0xF0000000 - -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ - -/* - * Hardware Reset Configuration Word - * if CLKIN is 66.000MHz, then - * CSB = 132MHz, CORE = 264MHz, DDRC = 264MHz, LBC = 132MHz - */ -#define CONFIG_SYS_HRCW_LOW (0x20000000 /* reserved, must be set */ |\ - HRCWL_DDR_TO_SCB_CLK_2X1 |\ - HRCWL_CSB_TO_CLKIN_2X1 |\ - HRCWL_CORE_TO_CSB_2X1) - -#define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0XFFF00100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_8BIT |\ - HRCWH_RL_EXT_LEGACY |\ - HRCWH_TSEC1M_IN_MII |\ - HRCWH_TSEC2M_IN_MII |\ - HRCWH_BIG_ENDIAN) - #define CONFIG_SYS_SICRH 0x00000000 #define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D) #define CONFIG_HWCONFIG -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK |\ - HID0_ENABLE_INSTRUCTION_CACHE |\ - HID0_DISABLE_DYNAMIC_POWER_MANAGMENT) - -#define CONFIG_SYS_HID2 (HID2_HBE | 0x00020000) - /* * Definitions for initial stack pointer and data area (in DCACHE ) */ @@ -76,25 +37,12 @@ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /* - * Local Bus LCRR and LBCR regs - */ -#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 -#define CONFIG_SYS_LBC_LBCR (0x00040000 |\ - (0xFF << LBCR_BMT_SHIFT) |\ - 0xF) - -#define CONFIG_SYS_LBC_MRTPR 0x20000000 - -/* * Internal Definitions */ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* * Manually set up DDR parameters, @@ -169,20 +117,7 @@ #define CONFIG_SYS_FLASH_BASE 0xFF800000 #define CONFIG_SYS_FLASH_SIZE 8 -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 - -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\ - BR_PS_8 |\ - BR_MS_GPCM |\ - BR_V) -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ - OR_GPCM_SCY_10 |\ - OR_GPCM_EHTR |\ - OR_GPCM_TRLX |\ - OR_GPCM_CSNT |\ - OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 #define CONFIG_SYS_MAX_FLASH_SECT 128 @@ -200,60 +135,24 @@ #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) #define NAND_CACHE_PAGES 64 -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E -#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM -#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM - -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE) |\ - (2<