X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fhrcon.h;h=8fb321178fa178c83f4b8077a21daa6cacfd1ea4;hb=023ff4b88dcec5faa3f9b841bae4d3d232b58ce2;hp=76b28e07f4ec5eb9efa1231d9a22845eec62ca37;hpb=73df96a38e693312bc2d5b565bc439f3b98e63ea;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 76b28e0..8fb3211 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -21,14 +21,10 @@ #define CONFIG_FSL_SERDES #define CONFIG_FSL_SERDES1 0xe3000 -#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ - /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ @@ -115,13 +111,6 @@ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 -#define CONFIG_SYS_LBC_LBCR 0x00040000 - -/* * FLASH on the Local Bus */ #if 1 @@ -140,14 +129,6 @@ #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -/* - * FPGA - */ -#define CONFIG_SYS_FPGA0_BASE 0xE0600000 -#define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ - - -#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE #define CONFIG_SYS_FPGA_DONE(k) 0x0010 #define CONFIG_SYS_FPGA_COUNT 1 @@ -422,8 +403,6 @@ void fpga_control_clear(unsigned int bus, int pin); #define CONFIG_ROOTPATH "/opt/nfsroot" #define CONFIG_BOOTFILE "uImage" -#define CONFIG_PREBOOT /* enable preboot variable */ - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS1\0" \