X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fhcu5.h;h=1214bc31b59e6ff6fdab72db72be2c10eaefea0a;hb=feaa43f3a8f465cbf01ffa1b23b6b52431819a52;hp=f95d78ec1670d80d18b6ad97456a965cdb4d0683;hpb=8f22b671ebc4c625dbd58be19d844069dcc9660e;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h
index f95d78e..1214bc3 100644
--- a/include/configs/hcu5.h
+++ b/include/configs/hcu5.h
@@ -73,7 +73,6 @@
  * Initial RAM & stack pointer
  *----------------------------------------------------------------------*/
 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache	*/
-#define CFG_INIT_RAM_OCM	1		/* OCM as init ram	*/
 #define CFG_INIT_RAM_ADDR	CFG_OCM_BASE	/* OCM			*/
 
 #define CFG_INIT_RAM_END	(4 << 10)
@@ -365,13 +364,6 @@
 #define HCU_CPLD_VERSION_REGISTER ( CFG_CPLD + 0x0F00000 )
 #define HCU_HW_VERSION_REGISTER   ( CFG_CPLD + 0x1400000 )
 
-/*-----------------------------------------------------------------------
- * Cache Configuration
- *----------------------------------------------------------------------*/
-#define CFG_DCACHE_SIZE		(32<<10)  /* For AMCC 440 CPUs			*/
-#define CFG_CACHELINE_SIZE	32	      /* ...			            */
-#define CFG_CACHELINE_SHIFT	5	      /* log base 2 of the above value	*/
-
 /*
  * Internal Definitions
  *