X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fgrpeach.h;h=8de4a36e931a310e5b53afedd84e2035673cfd21;hb=6786ce1ce14feb4d02854a0c04bc0cce505be46e;hp=347845f1d501d49d8ea69132e66d95e644e5d848;hpb=037ef53cf01c522073a0a930c84c3ca858f032e1;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h
index 347845f..8de4a36 100644
--- a/include/configs/grpeach.h
+++ b/include/configs/grpeach.h
@@ -11,22 +11,17 @@
 /* Board Clock , P1 clock frequency (XTAL=13.33MHz) */
 
 /* Miscellaneous */
-#define CONFIG_SYS_PBSIZE	256
 
 /* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */
-#define CONFIG_SYS_SDRAM_BASE		0x20000000
-#define CONFIG_SYS_SDRAM_SIZE		(10 * 1024 * 1024)
-#define CONFIG_SYS_INIT_SP_ADDR		\
-	(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 1024 * 1024)
-
-#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CFG_SYS_SDRAM_BASE		0x20000000
+#define CFG_SYS_SDRAM_SIZE		(10 * 1024 * 1024)
 
 /* Network interface */
-#define CONFIG_SH_ETHER_USE_PORT	0
-#define CONFIG_SH_ETHER_PHY_ADDR	0
-#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
-#define CONFIG_SH_ETHER_CACHE_WRITEBACK
-#define CONFIG_SH_ETHER_CACHE_INVALIDATE
-#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
+#define CFG_SH_ETHER_USE_PORT	0
+#define CFG_SH_ETHER_PHY_ADDR	0
+#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
+#define CFG_SH_ETHER_CACHE_WRITEBACK
+#define CFG_SH_ETHER_CACHE_INVALIDATE
+#define CFG_SH_ETHER_ALIGNE_SIZE	64
 
 #endif	/* __GRPEACH_H */