X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fexynos5-common.h;h=9297fbdc08176445baf2c00797edd7f3de0c7438;hb=7d080773347c1f6e0e896d9284134a2a411155d6;hp=b2ff4dd9277d2327526b535966a9c7b01b3e1a62;hpb=f4c6f9335c1e867862dcebcfa9c05b2e3dd05636;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index b2ff4dd..9297fbd 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -1,9 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2013 Samsung Electronics * * Configuration settings for the SAMSUNG EXYNOS5 board. - * - * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_EXYNOS5_COMMON_H @@ -13,12 +12,10 @@ #include "exynos-common.h" -#define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_EXYNOS_SPL #ifdef FTRACE #define CONFIG_TRACE -#define CONFIG_CMD_TRACE #define CONFIG_TRACE_BUFFER_SIZE (16 << 20) #define CONFIG_TRACE_EARLY_SIZE (8 << 20) #define CONFIG_TRACE_EARLY @@ -27,7 +24,6 @@ /* Enable ACE acceleration for SHA1 and SHA256 */ #define CONFIG_EXYNOS_ACE_SHA -#define CONFIG_SHA_HW_ACCEL /* Power Down Modes */ #define S5P_CHECK_SLEEP 0x00000BAD @@ -41,35 +37,18 @@ #define INFORM3_OFFSET 0x80c /* select serial console configuration */ -#define CONFIG_BAUDRATE 115200 #define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 -#define CONFIG_SILENT_CONSOLE -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_CONSOLE_MUX - -#define CONFIG_CMD_HASH /* Thermal Management Unit */ #define CONFIG_EXYNOS_TMU -#define CONFIG_CMD_DTT -#define CONFIG_TMU_CMD_DTT /* MMC SPL */ #define COPY_BL2_FNPTR_ADDR 0x02020030 -#define CONFIG_SUPPORT_EMMC_BOOT - -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_GPIO_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT /* specific .lds file */ -#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" /* Boot Argument Buffer Size */ /* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) #define CONFIG_RD_LVL @@ -93,8 +72,6 @@ #define CONFIG_SYS_MONITOR_BASE 0x00000000 -#define CONFIG_SYS_MMC_ENV_DEV 0 - #define CONFIG_SECURE_BL1_ONLY /* Secure FW size configuration */ @@ -108,7 +85,6 @@ #define CONFIG_RES_BLOCK_SIZE (512) #define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ #define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */ -#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ #define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE) #define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE) @@ -124,47 +100,17 @@ #define CONFIG_SYS_I2C_S3C24X0 #define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */ #define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0 -#define CONFIG_I2C_EDID /* SPI */ -#ifdef CONFIG_SPI_FLASH -#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 -#define CONFIG_SF_DEFAULT_SPEED 50000000 -#endif - -#ifdef CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SPI_MODE SPI_MODE_0 -#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -#define CONFIG_ENV_SPI_BUS 1 -#define CONFIG_ENV_SPI_MAX_HZ 50000000 -#endif /* Ethernet Controllor Driver */ #ifdef CONFIG_CMD_NET -#define CONFIG_SMC911X -#define CONFIG_SMC911X_BASE 0x5000000 -#define CONFIG_SMC911X_16_BIT #define CONFIG_ENV_SROM_BANK 1 #endif /*CONFIG_CMD_NET*/ -/* SHA hashing */ -#define CONFIG_CMD_HASH -#define CONFIG_HASH_VERIFY -#define CONFIG_SHA1 -#define CONFIG_SHA256 - /* Enable Time Command */ /* USB */ -#define CONFIG_USB_STORAGE -#define CONFIG_USB_XHCI_DWC3 -#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 -#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 - -#define CONFIG_USB_HOST_ETHER -#define CONFIG_USB_ETHER_ASIX -#define CONFIG_USB_ETHER_SMSC95XX -#define CONFIG_USB_ETHER_RTL8152 /* USB boot mode */ #define CONFIG_USB_BOOTING @@ -173,6 +119,7 @@ #define EXYNOS_IRAM_SECONDARY_BASE 0x02020018 #define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 2) \ func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ func(PXE, pxe, na) \