X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fethernut5.h;h=182369def910c1a530060f9acf3de927e15876e5;hb=6786ce1ce14feb4d02854a0c04bc0cce505be46e;hp=7a3c800dca9c1150bc35f666c3f7ca9515b212c2;hpb=b8e09898919e23c5d7f1934be7bf9a3a6f0deb0e;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h
index 7a3c800..182369d 100644
--- a/include/configs/ethernut5.h
+++ b/include/configs/ethernut5.h
@@ -18,53 +18,50 @@
 /* CPU information */
 
 /* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK	32768	/* slow clock xtal */
-#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000 /* 18.432 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK	32768	/* slow clock xtal */
+#define CFG_SYS_AT91_MAIN_CLOCK	18432000 /* 18.432 MHz crystal */
 
 /* 32kB internal SRAM */
-#define CONFIG_SYS_INIT_RAM_ADDR	0x00300000 /*AT91SAM9XE_SRAM_BASE */
-#define CONFIG_SYS_INIT_RAM_SIZE	(32 << 10)
+#define CFG_SYS_INIT_RAM_ADDR	0x00300000 /*AT91SAM9XE_SRAM_BASE */
+#define CFG_SYS_INIT_RAM_SIZE	(32 << 10)
 
 /* 128MB SDRAM in 1 bank */
-#define CONFIG_SYS_SDRAM_BASE		0x20000000
-#define CONFIG_SYS_SDRAM_SIZE		(128 << 20)
+#define CFG_SYS_SDRAM_BASE		0x20000000
+#define CFG_SYS_SDRAM_SIZE		(128 << 20)
 
 /* 512kB on-chip NOR flash */
-# define CONFIG_SYS_FLASH_BASE		0x00200000 /* AT91SAM9XE_FLASH_BASE */
+# define CFG_SYS_FLASH_BASE		0x00200000 /* AT91SAM9XE_FLASH_BASE */
 
 
 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_SYS_NAND_BASE		0x40000000
-#define CONFIG_SYS_NAND_DBW_8
+#define CFG_SYS_NAND_BASE		0x40000000
 /* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+#define CFG_SYS_NAND_MASK_ALE	(1 << 21)
 /* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PC(14)
+#define CFG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PC(14)
 #endif
 
 /* JFFS2 */
 
 /* Ethernet */
-#define CONFIG_PHY_ID			0
-#define CONFIG_MACB_SEARCH_PHY
+#define CFG_PHY_ID			0
 
 /* MMC */
 #ifdef CONFIG_CMD_MMC
-#define CONFIG_SYS_MMC_CD_PIN		AT91_PIO_PORTC, 8
+#define CFG_SYS_MMC_CD_PIN		AT91_PIO_PORTC, 8
 #endif
 
 /* RTC */
 #if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP)
-#define CONFIG_SYS_I2C_RTC_ADDR		0x51
+#define CFG_SYS_I2C_RTC_ADDR		0x51
 #endif
 
 /* I2C */
-#define CONFIG_SYS_MAX_I2C_BUS	1
+#define CFG_SYS_MAX_I2C_BUS	1
 
 #define I2C_SOFT_DECLARATIONS