X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fedminiv2.h;h=d2f1cd5d5c8cdf468f78945c2e678f5b3d0de4dc;hb=46b5c8ed017958fc387ab86c71ae6c90abb6793c;hp=664d6d1f340fb62ba67a70daa1d3860675a0c597;hpb=2ffa0e87df3a7595f71d05782924ee83146d9fe7;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
index 664d6d1..d2f1cd5 100644
--- a/include/configs/edminiv2.h
+++ b/include/configs/edminiv2.h
@@ -15,12 +15,6 @@
  * SPL
  */
 
-#define CONFIG_SPL_MAX_SIZE		0x0000fff0
-#define CONFIG_SPL_STACK		0x00020000
-#define CONFIG_SPL_BSS_START_ADDR	0x00020000
-#define CONFIG_SPL_BSS_MAX_SIZE		0x0001ffff
-#define CONFIG_SYS_SPL_MALLOC_START	0x00040000
-#define CONFIG_SYS_SPL_MALLOC_SIZE	0x0001ffff
 #define CONFIG_SYS_UBOOT_BASE		0xfff90000
 #define CONFIG_SYS_UBOOT_START		0x00800000
 
@@ -28,9 +22,6 @@
  * High Level Configuration Options (easy to change)
  */
 
-#define CONFIG_FEROCEON		1	/* CPU Core subversion */
-#define CONFIG_88F5182		1	/* SOC Name */
-
 #include <asm/arch/orion5x.h>
 /*
  * CLKs configurations
@@ -88,14 +79,10 @@
  * FLASH configuration
  */
 
-#define CONFIG_SYS_MAX_FLASH_BANKS	1  /* max num of flash banks       */
-#define CONFIG_SYS_MAX_FLASH_SECT	11 /* max num of sects on one chip */
 #define CONFIG_SYS_FLASH_BASE		0xfff80000
 
 /* auto boot */
 
-#define	CONFIG_SYS_CBSIZE	1024	/* Console I/O Buff Size */
-
 /*
  * Network
  */
@@ -104,8 +91,6 @@
 #define CONFIG_MVGBE_PORTS	{1}		/* enable port 0 only */
 #define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION	/* don't randomize MAC */
 #define CONFIG_PHY_BASE_ADR	0x8
-#define CONFIG_RESET_PHY_R	/* use reset_phy() to init mv8831116 PHY */
-#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
 #endif
 
 /*
@@ -113,23 +98,11 @@
  */
 #ifdef CONFIG_IDE
 #define __io
-/* Needs byte-swapping for ATA data register */
-#define CONFIG_IDE_SWAP_IO
 /* Data, registers and alternate blocks are at the same offset */
-#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0100)
-#define CONFIG_SYS_ATA_REG_OFFSET	(0x0100)
-#define CONFIG_SYS_ATA_ALT_OFFSET	(0x0100)
 /* Each 8-bit ATA register is aligned to a 4-bytes address */
-#define CONFIG_SYS_ATA_STRIDE		4
-/* Controller supports 48-bits LBA addressing */
-#define CONFIG_LBA48
 /* A single bus, a single device */
-#define CONFIG_SYS_IDE_MAXBUS		1
-#define CONFIG_SYS_IDE_MAXDEVICE	1
 /* ATA registers base is at SATA controller base */
-#define CONFIG_SYS_ATA_BASE_ADDR	ORION5X_SATA_BASE
 /* ATA bus 0 is orion5x port 1 on ED Mini V2 */
-#define CONFIG_SYS_ATA_IDE0_OFFSET	ORION5X_SATA_PORT1_OFFSET
 /* end of IDE defines */
 #endif /* CMD_IDE */
 
@@ -157,7 +130,5 @@
 
 /* additions for new relocation code, must be added to all boards */
 #define CONFIG_SYS_SDRAM_BASE		0
-#define CONFIG_SYS_INIT_SP_ADDR	\
-	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
 
 #endif /* _CONFIG_EDMINIV2_H */