X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fedb93xx.h;h=efe2a9daa7c150d16c172b596b76aed8ce2cacb8;hb=181bd9dc61d2da88b78f1c1138a685dae39354d6;hp=4b00391a09f626e390b00320dd92bb4bb1c4f18d;hpb=bdaef38171c9ea030bae46b798aba4f430dcac18;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h index 4b00391..efe2a9d 100644 --- a/include/configs/edb93xx.h +++ b/include/configs/edb93xx.h @@ -36,6 +36,10 @@ #define CONFIG_SYS_HUSH_PARSER 1 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_SYS_LDSCRIPT "board/cirrus/edb93xx/u-boot.lds" + +#undef CONFIG_SYS_PROMPT #ifdef CONFIG_EDB9301 #define CONFIG_EP9301 #define CONFIG_MACH_TYPE MACH_TYPE_EDB9301 @@ -60,7 +64,7 @@ #define CONFIG_EP9307 #define CONFIG_MACH_TYPE MACH_TYPE_EDB9307A #define CONFIG_SYS_PROMPT "EDB9307A> " -#define CONFIG_ENV_SECT_SIZE 0x00040000 +#define CONFIG_ENV_SECT_SIZE 0x00020000 #elif defined(CONFIG_EDB9312) #define CONFIG_EP9312 #define CONFIG_MACH_TYPE MACH_TYPE_EDB9312 @@ -75,28 +79,20 @@ #define CONFIG_EP9315 #define CONFIG_MACH_TYPE MACH_TYPE_EDB9315A #define CONFIG_SYS_PROMPT "EDB9315A> " -#define CONFIG_ENV_SECT_SIZE 0x00040000 +#define CONFIG_ENV_SECT_SIZE 0x00020000 #else #error "no board defined" #endif /* High-level configuration options */ -#define CONFIG_ARM920T 1 /* This is an ARM920T core... */ -#define CONFIG_EP93XX 1 /* in a Cirrus Logic 93xx SoC */ +#define CONFIG_EP93XX 1 /* This is a Cirrus Logic 93xx SoC */ #define CONFIG_SYS_CLK_FREQ 14745600 /* EP93xx has a 14.7456 clock */ -#define CONFIG_SYS_HZ 1000 /* decr freq: 1 ms ticks */ -#undef CONFIG_USE_IRQ /* Don't need IRQ/FIQ */ +#undef CONFIG_USE_IRQ /* Don't need IRQ/FIQ */ /* Monitor configuration */ -#include -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_SETGETDCR -#undef CONFIG_CMD_XIMG - #undef CONFIG_CMD_DATE #define CONFIG_CMD_DHCP -#define CONFIG_CMD_FAT #define CONFIG_CMD_JFFS2 #define CONFIG_SYS_LONGHELP /* Enable "long" help in mon */ @@ -111,11 +107,14 @@ #define CONFIG_PL010_SERIAL #define CONFIG_CONS_INDEX 0 #define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, \ + 115200, 230400} #define CONFIG_SYS_SERIAL0 0x808C0000 #define CONFIG_SYS_SERIAL1 0x808D0000 -#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ - (void *)CONFIG_SYS_SERIAL1} +/*#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1} */ + +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0} /* Status LED */ #define CONFIG_STATUS_LED 1 /* Status LED enabled */ @@ -138,81 +137,55 @@ #define CONFIG_MII_SUPPRESS_PREAMBLE #define CONFIG_MII #define CONFIG_PHY_ADDR 1 -#define CONFIG_NET_MULTI -#undef CONFIG_NETCONSOLE +#undef CONFIG_NETCONSOLE /* SDRAM configuration */ -#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) +#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \ + defined(CONFIG_EDB9307) || defined CONFIG_EDB9312 || \ + defined(CONFIG_EDB9315) /* * EDB9301/2 has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75 * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set * the SROMLL bit on the processor, resulting in this non-contiguous memory map. - */ -#define CONFIG_NR_DRAM_BANKS 4 -#define PHYS_SDRAM_1 0x00000000 -#define PHYS_SDRAM_SIZE_1 0x00800000 -#define PHYS_SDRAM_2 0x01000000 -#define PHYS_SDRAM_SIZE_2 0x00800000 -#define PHYS_SDRAM_3 0x04000000 -#define PHYS_SDRAM_SIZE_3 0x00800000 -#define PHYS_SDRAM_4 0x05000000 -#define PHYS_SDRAM_SIZE_4 0x00800000 -#define CONFIG_EDB93XX_SDCS3 -#define CONFIG_SYS_MEMTEST_START 0x00100000 -#define CONFIG_SYS_MEMTEST_END 0x007fffff - -#elif defined(CONFIG_EDB9302A) -/* - * EDB9302a has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75 - * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set - * the SROMLL bit on the processor, resulting in this non-contiguous memory map. - */ -#define CONFIG_NR_DRAM_BANKS 4 -#define PHYS_SDRAM_1 0xc0000000 -#define PHYS_SDRAM_SIZE_1 0x00800000 -#define PHYS_SDRAM_2 0xc1000000 -#define PHYS_SDRAM_SIZE_2 0x00800000 -#define PHYS_SDRAM_3 0xc4000000 -#define PHYS_SDRAM_SIZE_3 0x00800000 -#define PHYS_SDRAM_4 0xc5000000 -#define PHYS_SDRAM_SIZE_4 0x00800000 -#define CONFIG_EDB93XX_SDCS0 -#define CONFIG_SYS_MEMTEST_START 0xc0100000 -#define CONFIG_SYS_MEMTEST_END 0xc07fffff - -#elif defined(CONFIG_EDB9307) || defined CONFIG_EDB9312 || \ - defined(CONFIG_EDB9315) -/* + * * The EDB9307, EDB9312, and EDB9315 have 2 banks of SDRAM consisting of * 2x Samsung K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of * 64 MB of SDRAM. */ -#define CONFIG_NR_DRAM_BANKS 2 -#define PHYS_SDRAM_1 0x00000000 -#define PHYS_SDRAM_SIZE_1 0x02000000 -#define PHYS_SDRAM_2 0x04000000 -#define PHYS_SDRAM_SIZE_2 0x02000000 + #define CONFIG_EDB93XX_SDCS3 -#define CONFIG_SYS_MEMTEST_START 0x00100000 -#define CONFIG_SYS_MEMTEST_END 0x01e00000 -#elif defined(CONFIG_EDB9307A) || defined(CONFIG_EDB9315A) +#elif defined(CONFIG_EDB9302A) || \ + defined(CONFIG_EDB9307A) || defined(CONFIG_EDB9315A) /* + * EDB9302a has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75 + * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set + * the SROMLL bit on the processor, resulting in this non-contiguous memory map. + * * The EDB9307A and EDB9315A have 2 banks of SDRAM consisting of 2x Samsung * K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of 64 MB of SDRAM. */ -#define CONFIG_NR_DRAM_BANKS 2 -#define PHYS_SDRAM_1 0xc0000000 -#define PHYS_SDRAM_SIZE_1 0x02000000 -#define PHYS_SDRAM_2 0xc4000000 -#define PHYS_SDRAM_SIZE_2 0x02000000 #define CONFIG_EDB93XX_SDCS0 -#define CONFIG_SYS_MEMTEST_START 0xc0100000 -#define CONFIG_SYS_MEMTEST_END 0xc1e00000 + +#else +#error "no SDCS configuration for this board" +#endif + + +#if defined(CONFIG_EDB93XX_SDCS3) +#define CONFIG_SYS_LOAD_ADDR 0x01000000 /* Default load address */ +#define PHYS_SDRAM_1 0x00000000 +#elif defined(CONFIG_EDB93XX_SDCS0) +#define CONFIG_SYS_LOAD_ADDR 0xc1000000 /* Default load address */ +#define PHYS_SDRAM_1 0xc0000000 #endif -/* Default load address */ -#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x01000000) +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_NR_DRAM_BANKS 8 + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 32*1024 - GENERATED_GBL_DATA_SIZE) + /* Must match kernel config */ #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) @@ -231,15 +204,16 @@ /* ----------------------------------------------------------------------------- * FLASH and environment organization * - * The EDB9301 and EDB9302(a) have 1 bank of flash memory at 0x60000000 - * consisting of 1x Intel TE28F128J3C-150 128 Mbit flash on a 16-bit data bus, - * for a total of 16 MB of CFI-compatible flash. + * The EDB9301, EDB9302(a), EDB9307a, EDB9315a have 1 bank of flash memory at + * 0x60000000 consisting of 1x Intel TE28F128J3C-150 128 Mbit flash on a 16-bit + * data bus, for a total of 16 MB of CFI-compatible flash. * - * The EDB9307(a), EDB9312, and EDB9315(a) have 1 bank of flash memory at + * The EDB9307, EDB9312, and EDB9315 have 1 bank of flash memory at * 0x60000000 consisting of 2x Micron MT28F128J3-12 128 Mbit flash on a 32-bit * data bus, for a total of 32 MB of CFI-compatible flash. * - * EDB9301/02(a) EDB9307(a)/12/15(a) + * + * EDB9301/02(a)7a/15a EDB9307/12/15 * 0x60000000 - 0x0003FFFF u-boot u-boot * 0x60040000 - 0x0005FFFF environment #1 environment #1 * 0x60060000 - 0x0007FFFF environment #2 environment #1 (continued) @@ -249,22 +223,62 @@ * 0x61000000 - 0x01FFFFFF not present unused */ #define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + + +#define CONFIG_SYS_FLASH_PROTECTION #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 128 +#define CONFIG_SYS_MAX_FLASH_SECT (256+8) + +#define CONFIG_SYS_TEXT_BASE 0x60000000 +#define PHYS_FLASH_1 CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE -#define PHYS_FLASH_1 0x60000000 -#define CONFIG_SYS_FLASH_BASE (PHYS_FLASH_1) #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_MONITOR_LEN (256 * 1024) #define CONFIG_ENV_OVERWRITE /* Vendor params unprotected */ #define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_ADDR 0x60040000 +#define CONFIG_ENV_ADDR 0x60040000 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE +/* Define to enable MMC on SPI support */ +/* #define CONFIG_EP93XX_SPI_MMC */ + +#ifdef CONFIG_EP93XX_SPI_MMC +#define CONFIG_EP93XX_SPI +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC_SPI +#define CONFIG_CMD_MMC +#define CONFIG_MMC_SPI_NPOWER_EGPIO 9 +#endif + +#define CONFIG_USB_STORAGE +#define CONFIG_USB_OHCI_NEW +#define CONFIG_USB_OHCI_EP93XX +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ep93xx-ohci" +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80020000 + +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_USB + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_CMD_BOOTZ + +/* Define to disable flash configuration*/ +/* #define CONFIG_EP93XX_NO_FLASH_CFG */ + +/* Define this for indusrial rated chips */ +/* #define CONFIG_EDB93XX_INDUSTRIAL */ + #endif /* !defined (__CONFIG_H) */