X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fdh_imx6.h;h=9231bd853f4afbd29ca8da2adb6565cd532aa31b;hb=29d280c88a1ff331dce2d4c7a5aaf2402aa0fd8a;hp=1f7fccad3fbce62f5a94c60c4d612fd325d809fe;hpb=ba8bf9481b0854fa7d48b0e9ed913c639f187c7d;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h
index 1f7fcca..9231bd8 100644
--- a/include/configs/dh_imx6.h
+++ b/include/configs/dh_imx6.h
@@ -1,9 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * DHCOM DH-iMX6 PDK board configuration
  *
  * Copyright (C) 2017 Marek Vasut <marex@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #ifndef __DH_IMX6_CONFIG_H
@@ -25,7 +24,6 @@
 /* SPL */
 #include "imx6_spl.h"			/* common IMX6 SPL configuration */
 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x11400
-#define CONFIG_SPL_SPI_LOAD
 #define CONFIG_SPL_TARGET		"u-boot-with-spl.imx"
 
 /* Miscellaneous configurable options */
@@ -35,18 +33,15 @@
 #define CONFIG_INITRD_TAG
 #define CONFIG_REVISION_TAG
 
-#define CONFIG_BOUNCE_BUFFER
 #define CONFIG_BZIP2
 
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(4 * SZ_1M)
 
 /* Bootcounter */
-#define CONFIG_SYS_BOOTCOUNT_ADDR	IRAM_BASE_ADDR
 #define CONFIG_SYS_BOOTCOUNT_BE
 
 /* FEC ethernet */
-#define CONFIG_MII
 #define IMX_FEC_BASE			ENET_BASE_ADDR
 #define CONFIG_FEC_XCV_TYPE		RMII
 #define CONFIG_ETHPRIME			"FEC"
@@ -67,7 +62,6 @@
 #define CONFIG_SYS_I2C_SPEED		100000
 
 /* MMC Configs */
-#define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR	0
 #define CONFIG_SYS_FSL_USDHC_NUM	3
@@ -92,7 +86,6 @@
 /* UART */
 #define CONFIG_MXC_UART
 #define CONFIG_MXC_UART_BASE		UART1_BASE
-#define CONFIG_CONS_INDEX		1
 #define CONFIG_BAUDRATE			115200
 
 /* USB Configs */
@@ -116,8 +109,6 @@
 #endif
 
 /* Watchdog */
-#define CONFIG_HW_WATCHDOG
-#define CONFIG_IMX_WATCHDOG
 #define CONFIG_WATCHDOG_TIMEOUT_MSECS	60000
 
 /* allow to overwrite serial and ethaddr */
@@ -152,7 +143,6 @@
 #endif
 
 /* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM