X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fdb-mv784mp-gp.h;h=7b305955c9629b15d9dd265d3cc80fe828661ca0;hb=a29491ade0adf3dbb9dc51be8b45530edde1f1df;hp=dbbc33ebf9c36bcf1d996da3ce63ba67a17589f9;hpb=5fac11e6d5ab350429b8c8ddf47d3d3877ca89d1;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h
index dbbc33e..7b30595 100644
--- a/include/configs/db-mv784mp-gp.h
+++ b/include/configs/db-mv784mp-gp.h
@@ -7,11 +7,6 @@
 #define _CONFIG_DB_MV7846MP_GP_H
 
 /*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_DB_784MP_GP		/* Board target name for DDR training */
-
-/*
  * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
  * for DDR ECC byte filling in the SPL before loading the main
  * U-Boot into it.
@@ -21,21 +16,11 @@
 #define CONFIG_I2C_MVTWSI_BASE0		MVEBU_TWSI_BASE
 
 /* USB/EHCI configuration */
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
 
 /* Environment in SPI NOR flash */
 
 #define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
 
-/* SATA support */
-#define CONFIG_SYS_SATA_MAX_DEVICE	2
-#define CONFIG_LBA48
-
-/* PCIe support */
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_PCI_SCAN_SHOW
-#endif
-
 /* NAND */
 
 /*
@@ -59,20 +44,8 @@
 
 /* SPL */
 /* Defines for SPL */
-#define CONFIG_SPL_MAX_SIZE		((128 << 10) - 0x4030)
-
-#define CONFIG_SPL_BSS_START_ADDR	(0x40000000 + (128 << 10))
-#define CONFIG_SPL_BSS_MAX_SIZE		(16 << 10)
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MALLOC_SIMPLE
-#endif
-
-#define CONFIG_SPL_STACK		(0x40000000 + ((192 - 16) << 10))
-#define CONFIG_SPL_BOOTROM_SAVE		(CONFIG_SPL_STACK + 4)
 
 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
 #define CONFIG_SPD_EEPROM		0x4e
-#define CONFIG_BOARD_ECC_SUPPORT	/* this board supports ECC */
 
 #endif /* _CONFIG_DB_MV7846MP_GP_H */