X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fdavinci_sonata.h;h=bb42a545852998608d0cba5982a9fe9c116a5464;hb=225f0eaa745adfae05931848543d99942798756a;hp=b2c0d7d175d67d7077e33d4ce76b5af32096f3df;hpb=2c78febd114b716714e7ac83c17bac5e30066512;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h
index b2c0d7d..bb42a54 100644
--- a/include/configs/davinci_sonata.h
+++ b/include/configs/davinci_sonata.h
@@ -60,24 +60,6 @@
 #define CFG_TIMERBASE		0x01c21400	/* use timer 0 */
 #define CFG_HZ_CLOCK		27000000	/* Timer Input clock freq */
 #define CFG_HZ			1000
-#define CFG_DAVINCI_PINMUX_0	0x00000c1f
-#define CFG_DAVINCI_WAITCFG	0x00000000
-#define CFG_DAVINCI_ACFG2	0x3ffffffd	/* CE configs */
-#define CFG_DAVINCI_ACFG3	0x3ffffffd
-#define CFG_DAVINCI_ACFG4	0x3ffffffd
-#define CFG_DAVINCI_ACFG5	0x3ffffffd
-#undef  CFG_DAVINCI_NANDCE    		/* When using NAND, define 2,3 or 4 */
-#define CFG_DAVINCI_DDRCTL	0x50006405	/* DDR timing config */
-#define CFG_DAVINCI_SDREF	0x000005c3
-#define CFG_DAVINCI_SDCFG	0x00178632	/* 8 banks */
-#define CFG_DAVINCI_SDTIM0	0x28923211
-#define CFG_DAVINCI_SDTIM1	0x0016c722
-#define CFG_DAVINCI_MMARG_BRF0	0x00444400
-/* DM6446 = 0x15, DM6441 = 0x12, DM6441_LV = 0x0e */
-#define CFG_DAVINCI_PLL1_PLLM	0x15
-#define CFG_DAVINCI_PLL2_PLLM	0x17		/* 162 MHz */
-#define CFG_DAVINCI_PLL2_DIV1	0x0b		/* 54 MHz */
-#define CFG_DAVINCI_PLL2_DIV2	0x01
 /*====================================================*/
 /* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
 /* on Sonata/DV_EVM board. No EEPROM on schmoogie.    */
@@ -130,18 +112,18 @@
 /* Flash & Environment */
 /*=====================*/
 #ifdef CFG_USE_NAND
-#undef CFG_ENV_IS_IN_FLASH
+#undef CONFIG_ENV_IS_IN_FLASH
 #define CFG_NO_FLASH
-#define CFG_ENV_IS_IN_NAND		/* U-Boot env in NAND Flash  */
-#define CFG_ENV_SECT_SIZE	512	/* Env sector Size */
-#define CFG_ENV_SIZE		SZ_16K
+#define CONFIG_ENV_IS_IN_NAND		/* U-Boot env in NAND Flash  */
+#define CONFIG_ENV_SECT_SIZE	512	/* Env sector Size */
+#define CONFIG_ENV_SIZE		SZ_16K
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is loaded by a bootloader */
 #define CONFIG_SKIP_RELOCATE_UBOOT	/* to a proper address, init done */
 #define CFG_NAND_BASE		0x02000000
 #define CFG_NAND_HW_ECC
 #define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices */
 #define NAND_MAX_CHIPS		1
-#define CFG_ENV_OFFSET		0x0	/* Block 0--not used by bootcode */
+#define CONFIG_ENV_OFFSET		0x0	/* Block 0--not used by bootcode */
 #define DEF_BOOTM		""
 #elif defined(CFG_USE_NOR)
 #ifdef CONFIG_NOR_UART_BOOT
@@ -151,23 +133,23 @@
 #undef CONFIG_SKIP_LOWLEVEL_INIT
 #undef CONFIG_SKIP_RELOCATE_UBOOT
 #endif
-#define CFG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_IS_IN_FLASH
 #undef CFG_NO_FLASH
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
 #define CFG_FLASH_CFI
 #define CFG_MAX_FLASH_BANKS	1		/* max number of flash banks */
 #define CFG_FLASH_SECT_SZ	0x20000		/* 128KB sect size AMD Flash */
-#define CFG_ENV_OFFSET		(CFG_FLASH_SECT_SZ*2)
-#define PHYS_FLASH_1		0x02000000	/* CS2 Base address 	 */
+#define CONFIG_ENV_OFFSET		(CFG_FLASH_SECT_SZ*2)
+#define PHYS_FLASH_1		0x02000000	/* CS2 Base address	 */
 #define CFG_FLASH_BASE		PHYS_FLASH_1	/* Flash Base for U-Boot */
-#define PHYS_FLASH_SIZE		0x2000000	/* Flash size 32MB 	 */
+#define PHYS_FLASH_SIZE		0x2000000	/* Flash size 32MB	 */
 #define CFG_MAX_FLASH_SECT	(PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ)
-#define CFG_ENV_SECT_SIZE	CFG_FLASH_SECT_SZ	/* Env sector Size */
+#define CONFIG_ENV_SECT_SIZE	CFG_FLASH_SECT_SZ	/* Env sector Size */
 #endif
 /*==============================*/
 /* U-Boot general configuration */
 /*==============================*/
-#undef 	CONFIG_USE_IRQ			/* No IRQ/FIQ in U-Boot */
+#undef	CONFIG_USE_IRQ			/* No IRQ/FIQ in U-Boot */
 #define CONFIG_MISC_INIT_R
 #undef CONFIG_BOOTDELAY
 #define CONFIG_BOOTFILE		"uImage"	/* Boot file name */