X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fda850evm.h;h=f7c5d400cf923b4ac7eb3e59a47e6b65f9d35288;hb=92832045c54586e9dffa082ff8cd8c2ef6040757;hp=2bb4e47496b483876168f835a833bc097f9cd2f2;hpb=50c9b0e1ddce280823484579c4ecc1f069e7833b;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 2bb4e47..f7c5d40 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -13,10 +13,6 @@ /* * Board */ -/* check if direct NOR boot config is used */ -#ifndef CONFIG_DIRECT_NOR_BOOT -#define CONFIG_USE_SPIFLASH -#endif /* * SoC Configuration @@ -26,16 +22,14 @@ #define CONFIG_SYS_OSCIN_FREQ 24000000 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) -#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY -#ifdef CONFIG_DIRECT_NOR_BOOT +#ifdef CONFIG_MTD_NOR_FLASH #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) #endif /* * Memory Info */ -#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ @@ -107,10 +101,6 @@ #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) -#ifdef CONFIG_USE_SPIFLASH -#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 -#endif - /* * I2C Configuration */ @@ -131,9 +121,6 @@ #undef CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST @@ -147,15 +134,8 @@ 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \ 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \ 59, 60, 61, 62, 63 } -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 10 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SPL_NAND_BASE -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_ECC -#define CONFIG_SPL_NAND_LOAD #ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_NAND_SELF_INIT @@ -166,11 +146,10 @@ * Network & Ethernet Configuration */ #ifdef CONFIG_DRIVER_TI_EMAC -#define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_NET_RETRY_COUNT 10 #endif -#ifdef CONFIG_USE_NOR +#ifdef CONFIG_MTD_NOR_FLASH #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE @@ -185,16 +164,12 @@ #define CONFIG_BOOTFILE "uImage" /* Boot file name */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) /* * Linux Information */ #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) #define CONFIG_HWCONFIG /* enable hwconfig */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_BOOTCOMMAND \ "run envboot; " \ @@ -223,23 +198,22 @@ #define CONFIG_CLOCKS #endif -#if !defined(CONFIG_MTD_RAW_NAND) && \ - !defined(CONFIG_USE_NOR) && \ - !defined(CONFIG_USE_SPIFLASH) -#endif - /* USB Configs */ #define CONFIG_USB_OHCI_NEW #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 -#ifndef CONFIG_DIRECT_NOR_BOOT +#ifndef CONFIG_MTD_NOR_FLASH +#define CONFIG_SPL_PAD_TO 32768 +#endif + +#ifdef CONFIG_SPL_BUILD /* defines for SPL */ #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ CONFIG_SYS_MALLOC_LEN) #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN #define CONFIG_SPL_STACK 0x8001ff00 #define CONFIG_SPL_MAX_FOOTPRINT 32768 -#define CONFIG_SPL_PAD_TO 32768 + #endif /* Load U-Boot Image From MMC */ @@ -247,12 +221,12 @@ /* additions for new relocation code, must added to all boards */ #define CONFIG_SYS_SDRAM_BASE 0xc0000000 -#ifdef CONFIG_DIRECT_NOR_BOOT +#ifdef CONFIG_MTD_NOR_FLASH #define CONFIG_SYS_INIT_SP_ADDR 0x8001ff00 #else #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ GENERATED_GBL_DATA_SIZE) -#endif /* CONFIG_DIRECT_NOR_BOOT */ +#endif /* CONFIG_MTD_NOR_FLASH */ #include