X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fcolibri_pxa270.h;h=622b02492dd2d2eeb0f1f5befa80fc37b7bc404c;hb=29d280c88a1ff331dce2d4c7a5aaf2402aa0fd8a;hp=d5255e7e0a135a281d871f1ebe18a9a1f9404660;hpb=3784c789e7e8de3d022ddf198b01e54b68971cd5;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h index d5255e7..622b024 100644 --- a/include/configs/colibri_pxa270.h +++ b/include/configs/colibri_pxa270.h @@ -1,10 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * Toradex Colibri PXA270 configuration file * * Copyright (C) 2010 Marek Vasut * Copyright (C) 2015-2016 Marcel Ziswiler - * - * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -14,21 +13,16 @@ * High Level Board Configuration Options */ #define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ -#define CONFIG_SYS_TEXT_BASE 0x0 /* Avoid overwriting factory configuration block */ #define CONFIG_BOARD_SIZE_LIMIT 0x40000 /* We will never enable dcache because we have to setup MMU first */ #define CONFIG_SYS_DCACHE_OFF -#define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */ - /* * Environment settings */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_ENV_VARS_UBOOT_CONFIG -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_SYS_MALLOC_LEN (128 * 1024) #define CONFIG_ARCH_CPU_INIT #define CONFIG_BOOTCOMMAND \ @@ -78,19 +72,9 @@ #define CONFIG_NET_RETRY_COUNT 10 #define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME #endif -#undef CONFIG_SYS_LONGHELP /* Saves 10 KB */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_DEVICE_NULLDEV 1 -#undef CONFIG_CMDLINE_EDITING /* Saves 2.5 KB */ -#undef CONFIG_AUTO_COMPLETE /* Saves 2.5 KB */ /* * Clock Configuration @@ -100,7 +84,6 @@ /* * DRAM Map */ -#define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */ #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ @@ -122,8 +105,6 @@ #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER 1 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT #define CONFIG_SYS_MAX_FLASH_SECT (4 + 255) @@ -133,9 +114,6 @@ #define CONFIG_SYS_FLASH_WRITE_TOUT (25 * CONFIG_SYS_HZ) #define CONFIG_SYS_FLASH_LOCK_TOUT (25 * CONFIG_SYS_HZ) #define CONFIG_SYS_FLASH_UNLOCK_TOUT (25 * CONFIG_SYS_HZ) - -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_FLASH_PROTECTION 1 #endif #define CONFIG_SYS_MONITOR_BASE 0x0