X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fcgtqmx8.h;h=91454df197207e7b763f4ed6e2778a05b9e0ba77;hb=6786ce1ce14feb4d02854a0c04bc0cce505be46e;hp=e4cac0062daf6ca72ce5bd4032d4668ead20a248;hpb=9b5f9aeb3b48dbc059272168635a397ea5096a31;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h
index e4cac00..91454df 100644
--- a/include/configs/cgtqmx8.h
+++ b/include/configs/cgtqmx8.h
@@ -12,24 +12,15 @@
 #include <asm/arch/imx-regs.h>
 
 #ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MONITOR_LEN				(1024 * 1024)
-
-#define CONFIG_SPL_STACK		0x013E000
-#define CONFIG_SPL_BSS_START_ADDR	0x00128000
-#define CONFIG_SYS_SPL_MALLOC_START	0x00120000
-#define CONFIG_SYS_SPL_MALLOC_SIZE	0x3000	/* 12 KB */
 #define CONFIG_SERIAL_LPUART_BASE	0x5a060000
-#define CONFIG_MALLOC_F_ADDR		0x00120000
-
-#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
+#define CFG_MALLOC_F_ADDR		0x00120000
 
-#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
 #endif
 
 /* Flat Device Tree Definitions */
 
-#define CONFIG_SYS_BOOTMAPSZ		(256 << 20)
-#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CFG_SYS_BOOTMAPSZ		(256 << 20)
+#define CFG_SYS_FSL_ESDHC_ADDR	0
 #define USDHC1_BASE_ADDR		0x5B010000
 #define USDHC2_BASE_ADDR		0x5B020000
 #define USDHC3_BASE_ADDR		0x5B030000
@@ -51,7 +42,7 @@
 #define FEC0_RESET IMX_GPIO_NR(2, 5)
 #define FEC0_PDOMAIN "conn_enet0"
 
-#define CONFIG_MFG_ENV_SETTINGS \
+#define CFG_MFG_ENV_SETTINGS \
 	"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
 		"rdinit=/linuxrc " \
 		"g_mass_storage.stall=0 g_mass_storage.removable=1 " \
@@ -64,8 +55,8 @@
 	"bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
 
 /* Initial environment variables */
-#define CONFIG_EXTRA_ENV_SETTINGS		\
-	CONFIG_MFG_ENV_SETTINGS \
+#define CFG_EXTRA_ENV_SETTINGS		\
+	CFG_MFG_ENV_SETTINGS \
 	M4_BOOT_ENV \
 	"script=boot.scr\0" \
 	"image=Image\0" \
@@ -118,17 +109,15 @@
 
 /* Link Definitions */
 
-#define CONFIG_SYS_INIT_SP_ADDR		0x80200000
-
-#define CONFIG_SYS_FSL_USDHC_NUM	3
+#define CFG_SYS_FSL_USDHC_NUM	3
 
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CFG_SYS_SDRAM_BASE		0x80000000
 #define PHYS_SDRAM_1			0x80000000
 #define PHYS_SDRAM_2			0x880000000
 #define PHYS_SDRAM_1_SIZE		0x80000000	/* 2 GB */
 #define PHYS_SDRAM_2_SIZE		0x100000000	/* 4 GB */
 
 /* Networking */
-#define CONFIG_FEC_MXC_PHYADDR		-1
+#define CFG_FEC_MXC_PHYADDR		-1
 
 #endif /* __CGTQMX8_H */