X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fbubinga.h;h=b02f86207a5df00f36981fd2bc612ed7803d5016;hb=1a4596601fd395f3afb8f82f3f840c5e00bdd57a;hp=627060a759116aa2c96d7a8cb026062cd6433af5;hpb=0f89c54be92773b23d66ac401ba6acb6144100c3;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h
index 627060a..b02f862 100644
--- a/include/configs/bubinga.h
+++ b/include/configs/bubinga.h
@@ -2,23 +2,7 @@
  * (C) Copyright 2000-2005
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+ 
  */
 
 /*
@@ -37,6 +21,8 @@
 #define CONFIG_4xx		1	/* ...member of PPC4xx family   */
 #define CONFIG_BUBINGA	        1	/* ...on a BUBINGA board	*/
 
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
+
 /*
  * Include common defines/options for all AMCC eval boards
  */
@@ -123,7 +109,7 @@
  * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
  * set Linux BASE_BAUD to 403200.
  */
-#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK           /* external serial clock */
 #undef  CONFIG_SYS_405_UART_ERRATA_59         /* 405GP/CR Rev. D silicon */
 #define CONFIG_SYS_BASE_BAUD       691200
@@ -151,6 +137,7 @@
 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 
 #define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
 #define CONFIG_PCI_HOST	PCI_HOST_FORCE  /* select pci host function     */
 #define CONFIG_PCI_PNP			/* do pci plug-and-play         */
 					/* resource configuration       */
@@ -179,6 +166,7 @@
  * (Set up by the startup code)
  */
 #define CONFIG_SYS_SRAM_BASE		0xFFF00000
+#define CONFIG_SYS_SRAM_SIZE		(256 << 10)
 #define CONFIG_SYS_FLASH_BASE		0xFFF80000
 
 /*-----------------------------------------------------------------------
@@ -235,10 +223,9 @@
 #define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
 
-#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
@@ -283,12 +270,12 @@
  * GPIO0[28-29] - UART1 data signal input/output
  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
  */
-#define CONFIG_SYS_GPIO0_OSRH          0x55555555
-#define CONFIG_SYS_GPIO0_OSRL          0x40000110
-#define CONFIG_SYS_GPIO0_ISR1H         0x00000000
-#define CONFIG_SYS_GPIO0_ISR1L         0x15555445
-#define CONFIG_SYS_GPIO0_TSRH          0x00000000
+#define CONFIG_SYS_GPIO0_OSRL          0x55555555
+#define CONFIG_SYS_GPIO0_OSRH          0x40000110
+#define CONFIG_SYS_GPIO0_ISR1L         0x00000000
+#define CONFIG_SYS_GPIO0_ISR1H         0x15555445
 #define CONFIG_SYS_GPIO0_TSRL          0x00000000
+#define CONFIG_SYS_GPIO0_TSRH          0x00000000
 #define CONFIG_SYS_GPIO0_TCR           0xFFFF8014
 
 /*-----------------------------------------------------------------------