X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fbubinga.h;h=b02f86207a5df00f36981fd2bc612ed7803d5016;hb=1a4596601fd395f3afb8f82f3f840c5e00bdd57a;hp=10c48143117c4fe643492876c9c5f479251adb88;hpb=5a753f98c6a01bd1c61a9a3f95e8329a35f62994;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h index 10c48143..b02f862 100644 --- a/include/configs/bubinga.h +++ b/include/configs/bubinga.h @@ -2,23 +2,7 @@ * (C) Copyright 2000-2005 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -37,6 +21,14 @@ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_BUBINGA 1 /* ...on a BUBINGA board */ +#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 + +/* + * Include common defines/options for all AMCC eval boards + */ +#define CONFIG_HOSTNAME bubinga +#include "amcc-common.h" + #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ @@ -75,153 +67,65 @@ * supported for backward compatibility. */ #if 1 -#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ #else -#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ +#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ #endif -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - +/* + * Default environment variables + */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=bubinga\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=/tftpboot/bubinga/uImage\0" \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_PPC \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ "kernel_addr=fff80000\0" \ "ramdisk_addr=fff90000\0" \ - "initrd_high=30000000\0" \ - "load=tftp 100000 /tftpboot/bubinga/u-boot.bin\0" \ - "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ - "cp.b 100000 fffc0000 40000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ "" -#define CONFIG_BOOTCOMMAND "run net_nfs" - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 1 /* PHY address */ +#define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 #define CONFIG_PHY1_ADDR 2 /* EMAC1 PHY address */ -#define CONFIG_NET_MULTI 1 -#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ #define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Bubinga */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_CACHE | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */ - /* - * Miscellaneous configurable options + * Commands additional to the ones defined in amcc-common.h */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_CMD_DATE +#define CONFIG_CMD_PCI +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_SNTP -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */ /* - * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1. - * If CFG_405_UART_ERRATA_59, then UART divisor is 31. - * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value. + * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. + * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. + * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value. * The Linux BASE_BAUD define should match this configuration. * baseBaud = cpuClock/(uartDivisor*16) - * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock, + * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, * set Linux BASE_BAUD to 403200. */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ -#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ -#define CFG_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ +#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ +#define CONFIG_SYS_BASE_BAUD 691200 /*----------------------------------------------------------------------- * I2C stuff *----------------------------------------------------------------------- */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */ +#define CONFIG_SYS_I2C_NOPROBES { 0x69 } /* avoid i2c probe hangup (why?) */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */ -#if (CONFIG_COMMANDS & CFG_CMD_EEPROM) -#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +#if defined(CONFIG_CMD_EEPROM) +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ #endif /*----------------------------------------------------------------------- @@ -233,89 +137,71 @@ #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ #define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ /* resource configuration */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ -#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ -#define CFG_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ -#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ +#define CONFIG_SYS_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */ +#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ +#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */ +#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */ +#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ /*----------------------------------------------------------------------- * External peripheral base address *----------------------------------------------------------------------- */ -#define CFG_KEY_REG_BASE_ADDR 0xF0100000 -#define CFG_IR_REG_BASE_ADDR 0xF0200000 -#define CFG_FPGA_REG_BASE_ADDR 0xF0300000 +#define CONFIG_SYS_KEY_REG_BASE_ADDR 0xF0100000 +#define CONFIG_SYS_IR_REG_BASE_ADDR 0xF0200000 +#define CONFIG_SYS_FPGA_REG_BASE_ADDR 0xF0300000 /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_SRAM_BASE 0xFFF00000 -#define CFG_FLASH_BASE 0xFFF80000 -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ -#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_SRAM_BASE 0xFFF00000 +#define CONFIG_SYS_SRAM_SIZE (256 << 10) +#define CONFIG_SYS_FLASH_BASE 0xFFF80000 /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CFG_FLASH_ADDR0 0x5555 -#define CFG_FLASH_ADDR1 0x2aaa -#define CFG_FLASH_WORD_SIZE unsigned char +#define CONFIG_SYS_FLASH_ADDR0 0x5555 +#define CONFIG_SYS_FLASH_ADDR1 0x2aaa +#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char -#ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ -#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ +#ifdef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) -#endif /* CFG_ENV_IS_IN_FLASH */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +#endif /* CONFIG_ENV_IS_IN_FLASH */ /*----------------------------------------------------------------------- * NVRAM organization */ -#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ -#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */ +#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ +#define CONFIG_SYS_NVRAM_SIZE 0x1ff8 /* NVRAM size */ -#ifdef CFG_ENV_IS_IN_NVRAM -#define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */ -#define CFG_ENV_ADDR \ - (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ -#endif -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405EP CPU */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#ifdef CONFIG_ENV_IS_IN_NVRAM +#define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */ +#define CONFIG_ENV_ADDR \ + (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */ #endif /* @@ -324,48 +210,47 @@ * BR0/1 and OR0/1 (FLASH) */ -#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ +#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ #define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in data cache) */ /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CFG_TEMP_STACK_OCM 1 +#define CONFIG_SYS_TEMP_STACK_OCM 1 /* On Chip Memory location */ -#define CFG_OCM_DATA_ADDR 0xF8000000 -#define CFG_OCM_DATA_SIZE 0x1000 -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ +#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 +#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ +#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup */ /* Memory Bank 0 (Flash/SRAM) initialization */ -#define CFG_EBC_PB0AP 0x04006000 -#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */ +#define CONFIG_SYS_EBC_PB0AP 0x04006000 +#define CONFIG_SYS_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */ /* Memory Bank 1 (NVRAM/RTC) initialization */ -#define CFG_EBC_PB1AP 0x04041000 -#define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ +#define CONFIG_SYS_EBC_PB1AP 0x04041000 +#define CONFIG_SYS_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ /* Memory Bank 2 (not used) initialization */ -#define CFG_EBC_PB2AP 0x00000000 -#define CFG_EBC_PB2CR 0x00000000 +#define CONFIG_SYS_EBC_PB2AP 0x00000000 +#define CONFIG_SYS_EBC_PB2CR 0x00000000 /* Memory Bank 2 (not used) initialization */ -#define CFG_EBC_PB3AP 0x00000000 -#define CFG_EBC_PB3CR 0x00000000 +#define CONFIG_SYS_EBC_PB3AP 0x00000000 +#define CONFIG_SYS_EBC_PB3CR 0x00000000 /* Memory Bank 4 (FPGA regs) initialization */ -#define CFG_EBC_PB4AP 0x01815000 -#define CFG_EBC_PB4CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ +#define CONFIG_SYS_EBC_PB4AP 0x01815000 +#define CONFIG_SYS_EBC_PB4CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ /*----------------------------------------------------------------------- * Definitions for Serial Presence Detect EEPROM address @@ -385,13 +270,13 @@ * GPIO0[28-29] - UART1 data signal input/output * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs */ -#define CFG_GPIO0_OSRH 0x55555555 -#define CFG_GPIO0_OSRL 0x40000110 -#define CFG_GPIO0_ISR1H 0x00000000 -#define CFG_GPIO0_ISR1L 0x15555445 -#define CFG_GPIO0_TSRH 0x00000000 -#define CFG_GPIO0_TSRL 0x00000000 -#define CFG_GPIO0_TCR 0xFFFF8014 +#define CONFIG_SYS_GPIO0_OSRL 0x55555555 +#define CONFIG_SYS_GPIO0_OSRH 0x40000110 +#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 +#define CONFIG_SYS_GPIO0_ISR1H 0x15555445 +#define CONFIG_SYS_GPIO0_TSRL 0x00000000 +#define CONFIG_SYS_GPIO0_TSRH 0x00000000 +#define CONFIG_SYS_GPIO0_TCR 0xFFFF8014 /*----------------------------------------------------------------------- * Some BUBINGA stuff... @@ -418,17 +303,4 @@ #define FPGA_REG1_OFFB_FLASH 0x02 /* Off board flash */ #define FPGA_REG1_SRAM_BOOT 0x01 /* SRAM at 0xFFF80000 not Flash */ -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - #endif /* __CONFIG_H */