X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fbf561-ezkit.h;h=0a309d926944e101e5e7e604a67d06e30867e21a;hb=7f14fb20f895016fb38d30ce71aeb4d441b5bcb8;hp=fca6e43b479bae9d7ef1cb58503610ff337f423d;hpb=78acc472d9719316f22e002a009a998d9ceec29d;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h
index fca6e43..0a309d9 100644
--- a/include/configs/bf561-ezkit.h
+++ b/include/configs/bf561-ezkit.h
@@ -60,7 +60,6 @@
  * Network Settings
  */
 #define ADI_CMDS_NETWORK	1
-#define CONFIG_NET_MULTI
 #define CONFIG_SMC91111	1
 #define CONFIG_SMC91111_BASE	0x2C010300
 #define CONFIG_SMC_USE_32_BIT	1
@@ -80,86 +79,35 @@
 #define CONFIG_SYS_MAX_FLASH_SECT	135
 /* The BF561-EZKIT uses a top boot flash */
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		0x20004000
-#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE	0x10000
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
-#define ENV_IS_EMBEDDED
-#else
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-#endif
-#ifdef ENV_IS_EMBEDDED
-/* WARNING - the following is hand-optimized to fit within
- * the sector before the environment sector. If it throws
- * an error during compilation remove an object here to get
- * it linked after the configuration sector.
- */
-# define LDS_BOARD_TEXT \
-	cpu/blackfin/traps.o		(.text .text.*); \
-	cpu/blackfin/interrupt.o	(.text .text.*); \
-	cpu/blackfin/serial.o		(.text .text.*); \
-	common/dlmalloc.o		(.text .text.*); \
-	lib/crc32.o		(.text .text.*); \
-	lib/zlib.o		(.text .text.*); \
-	board/bf561-ezkit/bf561-ezkit.o	(.text .text.*); \
-	. = DEFINED(env_offset) ? env_offset : .; \
-	common/env_embedded.o		(.text .text.*);
-#endif
+#define CONFIG_ENV_OFFSET	(0x800000 - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_SECT_SIZE	0x2000
 
 
 /*
  * I2C Settings
  */
-#define CONFIG_SOFT_I2C
-#ifdef CONFIG_SOFT_I2C
-#define PF_SCL PF0
-#define PF_SDA PF1
-#define I2C_INIT \
-	do { \
-		*pFIO0_DIR |= PF_SCL; \
-		SSYNC(); \
-	} while (0)
-#define I2C_ACTIVE \
-	do { \
-		*pFIO0_DIR |= PF_SDA; \
-		*pFIO0_INEN &= ~PF_SDA; \
-		SSYNC(); \
-	} while (0)
-#define I2C_TRISTATE \
-	do { \
-		*pFIO0_DIR &= ~PF_SDA; \
-		*pFIO0_INEN |= PF_SDA; \
-		SSYNC(); \
-	} while (0)
-#define I2C_READ ((*pFIO0_FLAG_D & PF_SDA) != 0)
-#define I2C_SDA(bit) \
-	do { \
-		if (bit) \
-			*pFIO0_FLAG_S = PF_SDA; \
-		else \
-			*pFIO0_FLAG_C = PF_SDA; \
-		SSYNC(); \
-	} while (0)
-#define I2C_SCL(bit) \
-	do { \
-		if (bit) \
-			*pFIO0_FLAG_S = PF_SCL; \
-		else \
-			*pFIO0_FLAG_C = PF_SCL; \
-		SSYNC(); \
-	} while (0)
+#define CONFIG_SYS_I2C_SOFT
+#ifdef CONFIG_SYS_I2C_SOFT
+#define CONFIG_SYS_I2C
+#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0
+#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1
 #define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
-
-#define CONFIG_SYS_I2C_SPEED		50000
-#define CONFIG_SYS_I2C_SLAVE		0
+#define CONFIG_SYS_I2C_SOFT_SPEED	50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0
 #endif
 
-
 /*
  * Misc Settings
  */
 #define CONFIG_UART_CONSOLE	0
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
+
+/*
+ * Run core 1 from L1 SRAM start address when init uboot on core 0
+ */
+/* #define CONFIG_CORE1_RUN	1 */
 
 
 /*