X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Faria.h;h=bd810538750b03df7524f76bcb0c1763e8798689;hb=842033e6964e9e5d34aca893c1845416dd8ac2cc;hp=58f67a4f0a1ae532c816a672a989bff231238244;hpb=92afd368bba7d98b2b7bfb51082c3639bb2119b3;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/aria.h b/include/configs/aria.h index 58f67a4..bd81053 100644 --- a/include/configs/aria.h +++ b/include/configs/aria.h @@ -49,7 +49,8 @@ #define CONFIG_E300 1 /* E300 Family */ #define CONFIG_MPC512X 1 /* MPC512X family */ #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ -#define CONFIG_FSL_DIU_LOGO_BMP 1 /* Don't include FSL DIU binary bmp */ + +#define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* video */ #undef CONFIG_VIDEO @@ -63,7 +64,6 @@ #define CONFIG_SYS_MPC512X_CLKIN 33000000 /* in Hz */ -#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */ #define CONFIG_MISC_INIT_R #define CONFIG_SYS_IMMR 0x80000000 @@ -78,6 +78,9 @@ #define CONFIG_SYS_DDR_SIZE 256 /* MB */ #define CONFIG_SYS_DDR_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 + +#define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000036 /* DDR Controller Configuration * @@ -123,26 +126,79 @@ * [09:05] DRAM tRP: * [04:00] DRAM tRPA */ -#define CONFIG_SYS_MDDRC_SYS_CFG 0xF8604A00 -#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xE8604A00 -/*#define CONFIG_SYS_MDDRC_TIME_CFG1 0x54EC1168 */ - #define CONFIG_SYS_MDDRC_TIME_CFG1 0x55D81189 -/*#define CONFIG_SYS_MDDRC_TIME_CFG2 0x35210864 */ - #define CONFIG_SYS_MDDRC_TIME_CFG2 0x34790863 - -#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000 -#define CONFIG_SYS_MDDRC_TIME_CFG0 0x00003D2E -/*#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x06183D2E */ -#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x030C3D2E - -#define CONFIG_SYS_MICRON_NOP 0x01380000 -#define CONFIG_SYS_MICRON_PCHG_ALL 0x01100400 -#define CONFIG_SYS_MICRON_EM2 0x01020000 -#define CONFIG_SYS_MICRON_EM3 0x01030000 -#define CONFIG_SYS_MICRON_EN_DLL 0x01010000 -#define CONFIG_SYS_MICRON_RFSH 0x01080000 +#define CONFIG_SYS_MDDRC_SYS_CFG ( (1 << 31) | /* RST_B */ \ + (1 << 30) | /* CKE */ \ + (1 << 29) | /* CLK_ON */ \ + (0 << 28) | /* CMD_MODE */ \ + (4 << 25) | /* DRAM_ROW_SELECT */ \ + (3 << 21) | /* DRAM_BANK_SELECT */ \ + (0 << 18) | /* SELF_REF_EN */ \ + (0 << 17) | /* 16BIT_MODE */ \ + (2 << 13) | /* RDLY */ \ + (0 << 12) | /* HALF_DQS_DLY */ \ + (1 << 11) | /* QUART_DQS_DLY */ \ + (2 << 8) | /* WDLY */ \ + (0 << 7) | /* EARLY_ODT */ \ + (1 << 6) | /* ON_DIE_TERMINATE */ \ + (0 << 5) | /* FIFO_OV_CLEAR */ \ + (0 << 4) | /* FIFO_UV_CLEAR */ \ + (0 << 1) | /* FIFO_OV_EN */ \ + (0 << 0) /* FIFO_UV_EN */ \ + ) + +#define CONFIG_SYS_MDDRC_TIME_CFG0 0x030C3D2E +#define CONFIG_SYS_MDDRC_TIME_CFG1 0x55D81189 +#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34790863 + +#define CONFIG_SYS_DDRCMD_NOP 0x01380000 +#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400 +#define CONFIG_SYS_MICRON_EMR ( (1 << 24) | /* CMD_REQ */ \ + (0 << 22) | /* DRAM_CS */ \ + (0 << 21) | /* DRAM_RAS */ \ + (0 << 20) | /* DRAM_CAS */ \ + (0 << 19) | /* DRAM_WEB */ \ + (1 << 16) | /* DRAM_BS[2:0] */ \ + (0 << 15) | /* */ \ + (0 << 12) | /* A12->out */ \ + (0 << 11) | /* A11->RDQS */ \ + (0 << 10) | /* A10->DQS# */ \ + (0 << 7) | /* OCD program */ \ + (0 << 6) | /* Rtt1 */ \ + (0 << 3) | /* posted CAS# */ \ + (0 << 2) | /* Rtt0 */ \ + (1 << 1) | /* ODS */ \ + (0 << 0) /* DLL */ \ + ) +#define CONFIG_SYS_MICRON_EMR2 0x01020000 +#define CONFIG_SYS_MICRON_EMR3 0x01030000 +#define CONFIG_SYS_DDRCMD_RFSH 0x01080000 #define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 -#define CONFIG_SYS_MICRON_OCD_DEFAULT 0x01010780 +#define CONFIG_SYS_MICRON_EMR_OCD ( (1 << 24) | /* CMD_REQ */ \ + (0 << 22) | /* DRAM_CS */ \ + (0 << 21) | /* DRAM_RAS */ \ + (0 << 20) | /* DRAM_CAS */ \ + (0 << 19) | /* DRAM_WEB */ \ + (1 << 16) | /* DRAM_BS[2:0] */ \ + (0 << 15) | /* */ \ + (0 << 12) | /* A12->out */ \ + (0 << 11) | /* A11->RDQS */ \ + (1 << 10) | /* A10->DQS# */ \ + (7 << 7) | /* OCD program */ \ + (0 << 6) | /* Rtt1 */ \ + (0 << 3) | /* posted CAS# */ \ + (1 << 2) | /* Rtt0 */ \ + (0 << 1) | /* ODS (Output Drive Strength) */ \ + (0 << 0) /* DLL */ \ + ) + +/* + * Backward compatible definitions, + * so we do not have to change arch/powerpc/cpu/mpc512x/fixed_sdram.c + */ +#define CONFIG_SYS_DDRCMD_EM2 (CONFIG_SYS_MICRON_EMR2) +#define CONFIG_SYS_DDRCMD_EM3 (CONFIG_SYS_MICRON_EMR3) +#define CONFIG_SYS_DDRCMD_EN_DLL (CONFIG_SYS_MICRON_EMR) +#define CONFIG_SYS_DDRCMD_OCD_DEFAULT (CONFIG_SYS_MICRON_EMR_OCD) /* DDR Priority Manager Configuration */ #define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 @@ -184,16 +240,41 @@ #undef CONFIG_SYS_FLASH_CHECKSUM +/* + * NAND FLASH support + * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only) + */ +#define CONFIG_CMD_NAND /* enable NAND support */ +#define CONFIG_JFFS2_NAND /* with JFFS2 on it */ +#define CONFIG_NAND_MPC5121_NFC +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +/* + * Configuration parameters for MPC5121 NAND driver + */ +#define CONFIG_FSL_NFC_WIDTH 1 +#define CONFIG_FSL_NFC_WRITE_SIZE 2048 +#define CONFIG_FSL_NFC_SPARE_SIZE 64 +#define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE + #define CONFIG_SYS_SRAM_BASE 0x30000000 #define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */ -#define CONFIG_SYS_ARIA_SRAM_BASE 0x30020000 -#define CONFIG_SYS_ARIA_SRAM_SIZE 0x20000 /* 128 KB */ +/* Make two SRAM regions contiguous */ +#define CONFIG_SYS_ARIA_SRAM_BASE (CONFIG_SYS_SRAM_BASE + \ + CONFIG_SYS_SRAM_SIZE) +#define CONFIG_SYS_ARIA_SRAM_SIZE 0x00100000 /* reserve 1MB-window */ +#define CONFIG_SYS_CS6_START CONFIG_SYS_ARIA_SRAM_BASE +#define CONFIG_SYS_CS6_SIZE CONFIG_SYS_ARIA_SRAM_SIZE #define CONFIG_SYS_ARIA_FPGA_BASE (CONFIG_SYS_ARIA_SRAM_BASE + \ CONFIG_SYS_ARIA_SRAM_SIZE) #define CONFIG_SYS_ARIA_FPGA_SIZE 0x20000 /* 128 KB */ +#define CONFIG_SYS_CS2_START CONFIG_SYS_ARIA_FPGA_BASE +#define CONFIG_SYS_CS2_SIZE CONFIG_SYS_ARIA_FPGA_SIZE + #define CONFIG_SYS_CS0_CFG 0x05059150 #define CONFIG_SYS_CS2_CFG ( (5 << 24) | \ (5 << 16) | \ @@ -218,15 +299,14 @@ /* Use SRAM for initial stack */ #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE -#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE +#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE -#define CONFIG_SYS_GBL_DATA_SIZE 0x100 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (384 * 1024) #ifdef CONFIG_FSL_DIU_FB #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) @@ -241,12 +321,12 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO /* * Serial console configuration */ #define CONFIG_PSC_CONSOLE 3 /* console on PSC3 */ +#define CONFIG_SYS_PSC3 #if CONFIG_PSC_CONSOLE != 3 #error CONFIG_PSC_CONSOLE must be 3 #endif @@ -264,13 +344,13 @@ /* Use the HUSH parser */ #define CONFIG_SYS_HUSH_PARSER #ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #endif /* * PCI */ #ifdef CONFIG_PCI +#define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_SYS_PCI_MEM_BASE 0xA0000000 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE @@ -293,7 +373,6 @@ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */ #define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_CMD_TREE /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SPEED 100000 @@ -305,7 +384,7 @@ /* * IIM - IC Identification Module */ -#undef CONFIG_IIM +#undef CONFIG_FSL_IIM /* * EEPROM configuration for Atmel AT24C32A-10TQ-2.7: @@ -320,7 +399,6 @@ * Ethernet configuration */ #define CONFIG_MPC512x_FEC 1 -#define CONFIG_NET_MULTI #define CONFIG_PHY_ADDR 0x17 #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_FEC_AN_TIMEOUT 1 @@ -352,6 +430,7 @@ #undef CONFIG_CMD_FUSE #define CONFIG_CMD_I2C #undef CONFIG_CMD_IDE +#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_MII #define CONFIG_CMD_NFS #define CONFIG_CMD_PING @@ -361,13 +440,39 @@ #define CONFIG_CMD_PCI #endif -#if defined(CONFIG_CMD_IDE) +#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2) #define CONFIG_DOS_PARTITION #define CONFIG_MAC_PARTITION #define CONFIG_ISO_PARTITION #endif /* defined(CONFIG_CMD_IDE) */ /* + * Dynamic MTD partition support + */ +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_FLASH_CFI_MTD +#define MTDIDS_DEFAULT "nor0=f8000000.flash,nand0=mpc5121.nand" + +/* + * NOR flash layout: + * + * F8000000 - FEAFFFFF 107 MiB User Data + * FEB00000 - FFAFFFFF 16 MiB Root File System + * FFB00000 - FFFEFFFF 4 MiB Linux Kernel + * FFF00000 - FFFBFFFF 768 KiB U-Boot (up to 512 KiB) and 2 x * env + * FFFC0000 - FFFFFFFF 256 KiB Device Tree + * + * NAND flash layout: one big partition + */ +#define MTDPARTS_DEFAULT "mtdparts=f8000000.flash:107m(user)," \ + "16m(rootfs)," \ + "4m(kernel)," \ + "768k(u-boot)," \ + "256k(dtb);" \ + "mpc5121.nand:-(data)" + +/* * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock. * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE * is set to 0xFFFF, watchdog timeouts after about 64s. For details @@ -401,10 +506,10 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Cache Configuration */ #define CONFIG_SYS_DCACHE_SIZE 32768 @@ -420,14 +525,6 @@ #define CONFIG_HIGH_BATS 1 /* High BATs supported */ -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 -#define BOOTFLAG_WARM 0x02 - #ifdef CONFIG_CMD_KGDB #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ @@ -440,8 +537,8 @@ #define CONFIG_TIMESTAMP #define CONFIG_HOSTNAME aria -#define CONFIG_BOOTFILE aria/uImage -#define CONFIG_ROOTPATH /opt/eldk/ppc_6xx +#define CONFIG_BOOTFILE "aria/uImage" +#define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx" #define CONFIG_LOADADDR 400000 /* default load addr */ @@ -460,9 +557,9 @@ "fdt_addr_r=880000\0" \ "ramdisk_addr_r=900000\0" \ "u-boot_addr=FFF00000\0" \ - "kernel_addr=FFC40000\0" \ - "fdt_addr=FFEC0000\0" \ - "ramdisk_addr=FC040000\0" \ + "kernel_addr=FFB00000\0" \ + "fdt_addr=FFFC0000\0" \ + "ramdisk_addr=FEB00000\0" \ "ramdiskfile=aria/uRamdisk\0" \ "u-boot=aria/u-boot.bin\0" \ "fdtfile=aria/aria.dtb\0" \ @@ -551,4 +648,21 @@ #define FSL_ATA_CTRL_DMA_WRITE 0x02000000 #define FSL_ATA_CTRL_IORDY_EN 0x01000000 +/* Clocks in use */ +#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ + CLOCK_SCCR1_LPC_EN | \ + CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ + CLOCK_SCCR1_PSCFIFO_EN | \ + CLOCK_SCCR1_DDR_EN | \ + CLOCK_SCCR1_FEC_EN | \ + CLOCK_SCCR1_NFC_EN | \ + CLOCK_SCCR1_PATA_EN | \ + CLOCK_SCCR1_PCI_EN | \ + CLOCK_SCCR1_TPR_EN) + +#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ + CLOCK_SCCR2_SPDIF_EN | \ + CLOCK_SCCR2_DIU_EN | \ + CLOCK_SCCR2_I2C_EN) + #endif /* __CONFIG_H */