X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fadvantech_dms-ba16.h;h=0c9de6125d97b7e304941452b67255f9530efc69;hb=d01806a8fcbdaedcc67cead56ece572021d97ab7;hp=f370fe5b7814f350d4f9db930941b3363cff5bea;hpb=76cc372879e2f2f0467e8a3875f097d189647793;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/advantech_dms-ba16.h b/include/configs/advantech_dms-ba16.h
index f370fe5..0c9de61 100644
--- a/include/configs/advantech_dms-ba16.h
+++ b/include/configs/advantech_dms-ba16.h
@@ -1,9 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright (C) 2016 Timesys Corporation
  * Copyright (C) 2016 Advantech Corporation
  * Copyright (C) 2012 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #ifndef __ADVANTECH_DMSBA16_CONFIG_H
@@ -33,7 +32,6 @@
 #define CONFIG_REVISION_TAG
 #define CONFIG_SYS_MALLOC_LEN		(10 * SZ_1M)
 
-#define CONFIG_MXC_GPIO
 #define CONFIG_MXC_UART
 
 #define CONFIG_MXC_OCOTP
@@ -45,10 +43,8 @@
 #define CONFIG_LBA48
 
 /* MMC Configs */
-#define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR      0
-#define CONFIG_BOUNCE_BUFFER
 
 /* USB Configs */
 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
@@ -57,11 +53,9 @@
 #define CONFIG_MXC_USB_FLAGS	0
 
 #define CONFIG_USBD_HS
-#define CONFIG_USB_FUNCTION_MASS_STORAGE
 
 /* Networking Configs */
 #define CONFIG_FEC_MXC
-#define CONFIG_MII
 #define IMX_FEC_BASE			ENET_BASE_ADDR
 #define CONFIG_FEC_XCV_TYPE		RGMII
 #define CONFIG_ETHPRIME		"FEC"
@@ -70,7 +64,6 @@
 
 /* Serial Flash */
 #ifdef CONFIG_CMD_SF
-#define CONFIG_MXC_SPI
 #define CONFIG_SF_DEFAULT_BUS		0
 #define CONFIG_SF_DEFAULT_CS		0
 #define CONFIG_SF_DEFAULT_SPEED	20000000
@@ -79,10 +72,8 @@
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX	1
 
 #define CONFIG_LOADADDR	0x12000000
-#define CONFIG_SYS_TEXT_BASE	0x17800000
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"script=boot.scr\0" \
@@ -203,8 +194,6 @@
 #define CONFIG_ARP_TIMEOUT     200UL
 
 /* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_AUTO_COMPLETE
 
 #define CONFIG_SYS_MEMTEST_START       0x10000000
 #define CONFIG_SYS_MEMTEST_END         0x10010000
@@ -212,10 +201,7 @@
 
 #define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
 
-#define CONFIG_CMDLINE_EDITING
-
 /* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS           1
 #define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
 
 #define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
@@ -237,9 +223,6 @@
 #define CONFIG_ENV_SPI_MODE             CONFIG_SF_DEFAULT_MODE
 #define CONFIG_ENV_SPI_MAX_HZ           CONFIG_SF_DEFAULT_SPEED
 
-#ifndef CONFIG_SYS_DCACHE_OFF
-#endif
-
 #define CONFIG_SYS_FSL_USDHC_NUM        3
 
 /* Framebuffer */