X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Facadia.h;h=9092a7c0962e5efea73d0d96d910a4c417c44f90;hb=f18fa31cdcfeecaf56e61224eb18d2f2b6d39d85;hp=c72d9339e6b09d80e4458eea8ee37ee7d8b735be;hpb=d7d5204ce2e0985ff2dfdf3a6b5b6a526cdb1c1e;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/acadia.h b/include/configs/acadia.h index c72d933..385e79c 100644 --- a/include/configs/acadia.h +++ b/include/configs/acadia.h @@ -2,23 +2,7 @@ * (C) Copyright 2007 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ /************************************************************************ @@ -32,13 +16,22 @@ * High Level Configuration Options *----------------------------------------------------------------------*/ #define CONFIG_ACADIA 1 /* Board is Acadia */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_405EZ 1 /* Specifc 405EZ support*/ + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xFFF80000 +#endif + +/* + * Include common defines/options for all AMCC eval boards + */ +#define CONFIG_HOSTNAME acadia +#include "amcc-common.h" + /* Detect Acadia PLL input clock automatically via CPLD bit */ -#define CONFIG_SYS_CLK_FREQ ((in8(CFG_CPLD_BASE + 0) == 0x0c) ? \ +#define CONFIG_SYS_CLK_FREQ ((in8(CONFIG_SYS_CPLD_BASE + 0) == 0x0c) ? \ 66666666 : 33333000) -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_F 1 /* Call misc_init_f */ #define CONFIG_NO_SERIAL_EEPROM @@ -59,291 +52,160 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (512 * 1024)/* Reserve 512 kB for malloc() */ - -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xfe000000 -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_CPLD_BASE 0x80000000 -#define CFG_NAND_ADDR 0xd0000000 -#define CFG_USB_HOST 0xef603000 /* USB OHCI 1.1 controller */ +#define CONFIG_SYS_FLASH_BASE 0xfe000000 +#define CONFIG_SYS_CPLD_BASE 0x80000000 +#define CONFIG_SYS_NAND_ADDR 0xd0000000 +#define CONFIG_SYS_USB_HOST 0xef603000 /* USB OHCI 1.1 controller */ /*----------------------------------------------------------------------- * Initial RAM & stack pointer *----------------------------------------------------------------------*/ -#define CFG_TEMP_STACK_OCM 1 /* OCM as init ram */ +#define CONFIG_SYS_TEMP_STACK_OCM 1 /* OCM as init ram */ /* On Chip Memory location */ -#define CFG_OCM_DATA_ADDR 0xF8000000 -#define CFG_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */ -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ +#define CONFIG_SYS_OCM_DATA_ADDR 0xf8000000 +#define CONFIG_SYS_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */ +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SRAM */ +#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* size for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ -#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ -#define CFG_BASE_BAUD 691200 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SERIAL_MULTI 1 - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ +#define CONFIG_SYS_BASE_BAUD 691200 /*----------------------------------------------------------------------- * Environment *----------------------------------------------------------------------*/ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) -#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#else -#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ -#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */ -#endif +#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ /*----------------------------------------------------------------------- * FLASH related *----------------------------------------------------------------------*/ -#define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ -#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ +#ifdef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) #endif /*----------------------------------------------------------------------- * RAM (CRAM) *----------------------------------------------------------------------*/ -#define CFG_MBYTES_RAM 64 /* 64MB */ +#define CONFIG_SYS_MBYTES_RAM 64 /* 64MB */ /*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_MULTI_EEPROMS -#define CFG_I2C_EEPROM_ADDR (0xa8>>1) -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_ENABLE -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 +#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 + +#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* I2C SYSMON (LM75, AD7414 is almost compatible) */ #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ #define CONFIG_DTT_AD7414 1 /* use AD7414 */ #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ -#define CFG_DTT_MAX_TEMP 70 -#define CFG_DTT_LOW_TEMP -30 -#define CFG_DTT_HYSTERESIS 3 - -#if 0 /* test-only... */ -/*----------------------------------------------------------------------- - * SPI stuff - Define to include SPI control - *----------------------------------------------------------------------- - */ -#define CONFIG_SPI -#endif +#define CONFIG_SYS_DTT_MAX_TEMP 70 +#define CONFIG_SYS_DTT_LOW_TEMP -30 +#define CONFIG_SYS_DTT_HYSTERESIS 3 /*----------------------------------------------------------------------- * Ethernet *----------------------------------------------------------------------*/ -#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_NET_MULTI 1 -#define CFG_RX_ETH_BUFFER 16 /* # of rx buffers & descriptors*/ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS +#define CONFIG_HAS_ETH0 1 +/* + * Default environment variables + */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=acadia\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=acadia/uImage\0" \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_PPC_OLD \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ "kernel_addr=fff10000\0" \ "ramdisk_addr=fff20000\0" \ - "initrd_high=30000000\0" \ - "load=tftp 200000 acadia/u-boot.bin\0" \ - "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ - "cp.b ${fileaddr} fffc0000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ "kozio=bootm ffc60000\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ #define CONFIG_USB_OHCI -#define CONFIG_USB_STORAGE /* Partitions */ -#define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION #define CONFIG_ISO_PARTITION #define CONFIG_SUPPORT_VFAT -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_DTT | \ - CFG_CMD_DIAG | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_FAT | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NAND | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_USB) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - *----------------------------------------------------------------------*/ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - /* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. + * Commands additional to the ones defined in amcc-common.h */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_CMD_DTT +#define CONFIG_CMD_NAND /*----------------------------------------------------------------------- * NAND FLASH *----------------------------------------------------------------------*/ -#define CFG_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 -#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS) -#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405EZ CPU */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/ -#endif +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) +#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup *----------------------------------------------------------------------*/ -#define CFG_NAND_CS 3 /* NAND chip connected to CSx */ - +#define CONFIG_SYS_NAND_CS 3 /* Memory Bank 0 (Flash) initialization */ -#define CFG_EBC_PB0AP 0x03337200 -#define CFG_EBC_PB0CR 0xfe0bc000 +#define CONFIG_SYS_EBC_PB0AP 0x03337200 +#define CONFIG_SYS_EBC_PB0CR 0xfe0bc000 + +/* Memory Bank 3 (NAND-FLASH) initialization */ +#define CONFIG_SYS_EBC_PB3AP 0x018003c0 +#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND_ADDR | 0x1c000) /* Just initial configuration for CRAM. Will be changed in memory.c to sync mode*/ /* Memory Bank 1 (CRAM) initialization */ -#define CFG_EBC_PB1AP 0x030400c0 -#define CFG_EBC_PB1CR 0x000bc000 +#define CONFIG_SYS_EBC_PB1AP 0x030400c0 +#define CONFIG_SYS_EBC_PB1CR 0x000bc000 /* Memory Bank 2 (CRAM) initialization */ -#define CFG_EBC_PB2AP 0x030400c0 -#define CFG_EBC_PB2CR 0x020bc000 - -/* Memory Bank 3 (NAND-FLASH) initialization */ -#define CFG_EBC_PB3AP 0x018003c0 -#define CFG_EBC_PB3CR (CFG_NAND_ADDR | 0x1c000) +#define CONFIG_SYS_EBC_PB2AP 0x030400c0 +#define CONFIG_SYS_EBC_PB2CR 0x020bc000 /* Memory Bank 4 (CPLD) initialization */ -#define CFG_EBC_PB4AP 0x04006000 -#define CFG_EBC_PB4CR (CFG_CPLD_BASE | 0x18000) +#define CONFIG_SYS_EBC_PB4AP 0x04006000 +#define CONFIG_SYS_EBC_PB4CR (CONFIG_SYS_CPLD_BASE | 0x18000) -#define CFG_EBC_CFG 0xf8400000 +#define CONFIG_SYS_EBC_CFG 0xf8400000 /*----------------------------------------------------------------------- * GPIO Setup *----------------------------------------------------------------------*/ -#define CFG_GPIO_CRAM_CLK 8 -#define CFG_GPIO_CRAM_WAIT 9 -#define CFG_GPIO_CRAM_ADV 10 -#define CFG_GPIO_CRAM_CRE (32 + 21) +#define CONFIG_SYS_GPIO_CRAM_CLK 8 +#define CONFIG_SYS_GPIO_CRAM_WAIT 9 /* GPIO-In */ +#define CONFIG_SYS_GPIO_CRAM_ADV 10 +#define CONFIG_SYS_GPIO_CRAM_CRE (32 + 21) /* GPIO-Out */ /*----------------------------------------------------------------------- * Definitions for GPIO_0 setup (PPC405EZ specific) @@ -365,13 +227,13 @@ * GPIO0[28-30] - Trace Outputs / PWM Inputs * GPIO0[31] - PWM_8 I/O */ -#define CFG_GPIO0_TCR 0xC0000000 -#define CFG_GPIO0_OSRL 0x50000000 -#define CFG_GPIO0_OSRH 0x02000055 -#define CFG_GPIO0_ISR1L 0x00000000 -#define CFG_GPIO0_ISR1H 0x00000055 -#define CFG_GPIO0_TSRL 0x02000000 -#define CFG_GPIO0_TSRH 0x00000055 +#define CONFIG_SYS_GPIO0_TCR 0xC0A00000 +#define CONFIG_SYS_GPIO0_OSRL 0x50004400 +#define CONFIG_SYS_GPIO0_OSRH 0x02000055 +#define CONFIG_SYS_GPIO0_ISR1L 0x00001000 +#define CONFIG_SYS_GPIO0_ISR1H 0x00000055 +#define CONFIG_SYS_GPIO0_TSRL 0x02000000 +#define CONFIG_SYS_GPIO0_TSRH 0x00000055 /*----------------------------------------------------------------------- * Definitions for GPIO_1 setup (PPC405EZ specific) @@ -387,25 +249,12 @@ * GPIO1[16] - SPI_SS_1_N Output * GPIO1[17-20] - Trace Output/External Interrupts IRQ0 - IRQ3 inputs */ -#define CFG_GPIO1_OSRH 0x55455555 -#define CFG_GPIO1_OSRL 0x40000110 -#define CFG_GPIO1_ISR1H 0x00000000 -#define CFG_GPIO1_ISR1L 0x15555445 -#define CFG_GPIO1_TSRH 0x00000000 -#define CFG_GPIO1_TSRL 0x00000000 -#define CFG_GPIO1_TCR 0xFFFF8014 - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ - #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif +#define CONFIG_SYS_GPIO1_TCR 0xFFFF8414 +#define CONFIG_SYS_GPIO1_OSRL 0x40000110 +#define CONFIG_SYS_GPIO1_OSRH 0x55455555 +#define CONFIG_SYS_GPIO1_ISR1L 0x15555445 +#define CONFIG_SYS_GPIO1_ISR1H 0x00000000 +#define CONFIG_SYS_GPIO1_TSRL 0x00000000 +#define CONFIG_SYS_GPIO1_TSRH 0x00000000 #endif /* __CONFIG_H */