X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FZPC1900.h;h=b04be766f5723e378bb0e9f8c93db4e1cc4a963c;hb=1a247ba7fa5fb09f56892a09a990f03ce564b3e2;hp=f71e691b262c417a3c4b3b9c5630b7d4f0085dad;hpb=05b47540aae996908e48e10a5ff8b69862aadef3;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/ZPC1900.h b/include/configs/ZPC1900.h index f71e691..b04be76 100644 --- a/include/configs/ZPC1900.h +++ b/include/configs/ZPC1900.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2003-2004 Arabella Software Ltd. + * Copyright (C) 2003-2005 Arabella Software Ltd. * Yuli Barcohen * * U-Boot configuration for Zephyr Engineering ZPC.1900 board. @@ -32,11 +32,7 @@ #define CPU_ID_STR "MPC8265" #define CONFIG_CPM2 1 /* Has a CPM2 */ -#undef DEBUG - -#undef CONFIG_BOARD_EARLY_INIT_F /* Don't call board_early_init_f */ - -/* Allow serial number (serial) and MAC address (ethaddr) to be overwritten */ +/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */ #define CONFIG_ENV_OVERWRITE /* @@ -59,8 +55,8 @@ * SCC, 1-3 for FCC) * * If CONFIG_ETHER_NONE is defined, then either the ethernet routines - * must be defined elsewhere (as for the console), or CFG_CMD_NET must - * be removed from CONFIG_COMMANDS to remove support for networking. + * must be defined elsewhere (as for the console), or CONFIG_CMD_NET + * must be unset. */ #undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ #define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ @@ -110,23 +106,33 @@ #define CONFIG_BAUDRATE 38400 -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_ASKENV \ - | CFG_CMD_DHCP \ - | CFG_CMD_ECHO \ - | CFG_CMD_IMMAP \ - | CFG_CMD_MII \ - | CFG_CMD_PING \ - ) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_IMMAP +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING + #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_BOOTCOMMAND "dhcp;bootm" /* autoboot command */ #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=:::::eth0:dhcp" -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ #undef CONFIG_KGDB_NONE /* define if kgdb on something else */ @@ -144,7 +150,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -154,31 +160,30 @@ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ +#define CFG_MEMTEST_END 0x03800000 /* 1 ... 56 MB in DRAM */ -#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_LOAD_ADDR 0x400000 /* default load address */ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } -#define CFG_FLASH_BASE 0xFFE00000 -#define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER -#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */ - -#define CFG_DEFAULT_IMMR 0x0F010000 - -#define CFG_IMMR 0xF0000000 #define CFG_SDRAM_BASE 0x00000000 #define CFG_SDRAM_SIZE 64 -#define CFG_FLSIMM_BASE 0xFC000000 -#define CFG_LSDRAM_BASE 0xFE000000 + +#define CFG_IMMR 0xF0000000 +#define CFG_LSDRAM_BASE 0xFC000000 +#define CFG_FLASH_BASE 0xFE000000 #define CFG_BCSR 0xFEA00000 #define CFG_EEPROM 0xFEB00000 +#define CFG_FLSIMM_BASE 0xFF000000 -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +#define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */ +#define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */ + +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLSIMM_BASE } #define BCSR_PCI_MODE 0x01 @@ -190,18 +195,18 @@ /* Hard reset configuration word */ #define CFG_HRCW_MASTER (HRCW_EBM | HRCW_BPS01| HRCW_CIP |\ - HRCW_L2CPC10 | HRCW_DPPC00 | HRCW_ISB010 |\ - HRCW_BMS | HRCW_LBPC01 | HRCW_APPC10 |\ - HRCW_MODCK_H0101 \ - ) /* 0x16828605 */ + HRCW_L2CPC10 | HRCW_DPPC00 | HRCW_ISB100 |\ + HRCW_BMS | HRCW_LBPC00 | HRCW_APPC10 |\ + HRCW_MODCK_H0111 \ + ) /* 0x16848207 */ /* No slaves */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ @@ -211,7 +216,7 @@ #define CFG_RAMBOOT #endif -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ @@ -229,18 +234,18 @@ #endif #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif -#define CFG_HID0_INIT 0 -#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE ) +#define CFG_HID0_INIT (HID0_ICFI) +#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE) #define CFG_HID2 0 #define CFG_SIUMCR 0x42200000 #define CFG_SYPCR 0xFFFFFFC3 -#define CFG_BCR 0x90400000 +#define CFG_BCR 0x90000000 #define CFG_SCCR SCCR_DFBRG01 #define CFG_RMR RMR_CSRE @@ -248,19 +253,24 @@ #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) #define CFG_RCCR 0 -#define CFG_PSDMR 0x014EB45A -#define CFG_PSRT 0x0C -#define CFG_LSDMR 0x008AB552 -#define CFG_LSRT 0x0E +#define CFG_PSDMR /* 0x834DA43B */0x014DA43A +#define CFG_PSRT 0x0F/* 0x0C */ +#define CFG_LSDMR 0x0085A562 +#define CFG_LSRT 0x0F #define CFG_MPTPR 0x4000 -#define CFG_BR0_PRELIM CFG_FLASH_BASE | 0x00000801 +#define CFG_PSDRAM_BR (CFG_SDRAM_BASE | 0x00000041) +#define CFG_PSDRAM_OR 0xFC0028C0 +#define CFG_LSDRAM_BR (CFG_LSDRAM_BASE | 0x00001861) +#define CFG_LSDRAM_OR 0xFF803480 + +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x00000801) #define CFG_OR0_PRELIM 0xFFE00856 -#define CFG_BR5_PRELIM CFG_EEPROM | 0x00000801 +#define CFG_BR5_PRELIM (CFG_EEPROM | 0x00000801) #define CFG_OR5_PRELIM 0xFFFF03F6 -#define CFG_BR6_PRELIM CFG_FLSIMM_BASE | 0x00000801 -#define CFG_OR6_PRELIM 0xFE000856 -#define CFG_BR7_PRELIM CFG_BCSR | 0x00000801 +#define CFG_BR6_PRELIM (CFG_FLSIMM_BASE | 0x00001801) +#define CFG_OR6_PRELIM 0xFF000856 +#define CFG_BR7_PRELIM (CFG_BCSR | 0x00000801) #define CFG_OR7_PRELIM 0xFFFF83F6 #define CFG_RESET_ADDRESS 0xC0000000