X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FUCP1020.h;h=c3cc72e13f7f6e871746195c721c0bdfce432507;hb=35bd70c5107f0cfa610b5c7074a7ee2a60d5d82f;hp=3b651fdd5c2b32603e612056e9d47335af2bde70;hpb=171510522eb3dd723d84ed21d800440d1276a91a;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h index 3b651fd..c3cc72e 100644 --- a/include/configs/UCP1020.h +++ b/include/configs/UCP1020.h @@ -1,11 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2013-2015 Arcturus Networks, Inc. - * http://www.arcturusnetworks.com/products/ucp1020/ + * Copyright 2013-2019 Arcturus Networks, Inc. + * https://www.arcturusnetworks.com/products/ucp1020/ * based on include/configs/p1_p2_rdb_pc.h * original copyright follows: * Copyright 2009-2011 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -14,11 +13,65 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include + +/*** Arcturus FirmWare Environment */ + +#define MAX_SERIAL_SIZE 15 +#define MAX_HWADDR_SIZE 17 + +#define MAX_FWENV_ADDR 4 + +#define FWENV_MMC 1 +#define FWENV_SPI_FLASH 2 +#define FWENV_NOR_FLASH 3 +/* + #define FWENV_TYPE FWENV_MMC + #define FWENV_TYPE FWENV_SPI_FLASH +*/ +#define FWENV_TYPE FWENV_NOR_FLASH + +#if (FWENV_TYPE == FWENV_MMC) +#define FWENV_ADDR1 -1 +#define FWENV_ADDR2 -1 +#define FWENV_ADDR3 -1 +#define FWENV_ADDR4 -1 +#define EMPY_CHAR 0 +#endif + +#if (FWENV_TYPE == FWENV_SPI_FLASH) +#ifndef CONFIG_SF_DEFAULT_SPEED +#define CONFIG_SF_DEFAULT_SPEED 1000000 +#endif +#ifndef CONFIG_SF_DEFAULT_MODE +#define CONFIG_SF_DEFAULT_MODE SPI_MODE0 +#endif +#ifndef CONFIG_SF_DEFAULT_CS +#define CONFIG_SF_DEFAULT_CS 0 +#endif +#ifndef CONFIG_SF_DEFAULT_BUS +#define CONFIG_SF_DEFAULT_BUS 0 +#endif +#define FWENV_ADDR1 (0x200 - sizeof(smac)) +#define FWENV_ADDR2 (0x400 - sizeof(smac)) +#define FWENV_ADDR3 (CONFIG_ENV_SECT_SIZE + 0x200 - sizeof(smac)) +#define FWENV_ADDR4 (CONFIG_ENV_SECT_SIZE + 0x400 - sizeof(smac)) +#define EMPY_CHAR 0xff +#endif + +#if (FWENV_TYPE == FWENV_NOR_FLASH) +#define FWENV_ADDR1 0xEC080000 +#define FWENV_ADDR2 -1 +#define FWENV_ADDR3 -1 +#define FWENV_ADDR4 -1 +#define EMPY_CHAR 0xff +#endif +/***********************************/ + #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #if defined(CONFIG_TARTGET_UCP1020T1) @@ -39,10 +92,6 @@ #define CONFIG_NETMASK 255.255.252.0 #define CONFIG_ETHPRIME "eTSEC3" -#ifndef CONFIG_SPI_FLASH -#endif -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT - #define CONFIG_SYS_L2_SIZE (256 << 10) #endif @@ -55,7 +104,6 @@ #define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR" #define CONFIG_TSEC1 -#define CONFIG_TSEC2 #define CONFIG_TSEC3 #define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 @@ -71,10 +119,6 @@ #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_ETHPRIME "eTSEC1" -#ifndef CONFIG_SPI_FLASH -#endif -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT - #define CONFIG_SYS_L2_SIZE (256 << 10) #endif @@ -82,14 +126,12 @@ #ifdef CONFIG_SDCARD #define CONFIG_RAMBOOT_SDCARD #define CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc #endif #ifdef CONFIG_SPIFLASH #define CONFIG_RAMBOOT_SPIFLASH #define CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc #endif @@ -103,10 +145,6 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #endif -#define CONFIG_MP - -#define CONFIG_ENV_OVERWRITE - #define CONFIG_SYS_SATA_MAX_DEVICE 2 #define CONFIG_LBA48 @@ -123,9 +161,6 @@ #define CONFIG_ENABLE_36BIT_PHYS -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x1fffffff - #define CONFIG_SYS_CCSRBAR 0xffe00000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR @@ -142,7 +177,6 @@ #define CONFIG_DDR_SPD #endif #define CONFIG_SYS_SPD_BUS_NUM 1 -#undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M #define CONFIG_CHIP_SELECTS_PER_CTRL 1 @@ -188,8 +222,6 @@ #define CONFIG_SYS_DDR_MODE_2 0x8000c000 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 -#undef CONFIG_CLOCKS_IN_MHZ - /* * Memory map * @@ -226,10 +258,7 @@ #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE #define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ @@ -299,14 +328,6 @@ #define CONFIG_SYS_I2C_NCT72_ADDR 0x4C #define CONFIG_SYS_I2C_IDT6V49205B 0x69 -/* - * eSPI - Enhanced SPI - */ -#define CONFIG_HARD_SPI - -#define CONFIG_SF_DEFAULT_SPEED 10000000 -#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 - #if defined(CONFIG_PCI) /* * General PCI @@ -341,55 +362,10 @@ /* * Environment */ -#ifdef CONFIG_ENV_FIT_UCBOOT - -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000) -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ - -#else - -#define CONFIG_ENV_SPI_BUS 0 -#define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_MAX_HZ 10000000 -#define CONFIG_ENV_SPI_MODE 0 - -#ifdef CONFIG_RAMBOOT_SPIFLASH - -#define CONFIG_ENV_SIZE 0x3000 /* 12KB */ -#define CONFIG_ENV_OFFSET 0x2000 /* 8KB */ -#define CONFIG_ENV_SECT_SIZE 0x1000 - -#if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT) -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE -#endif - -#elif defined(CONFIG_RAMBOOT_SDCARD) +#if !defined(CONFIG_ENV_FIT_UCBOOT) && defined(CONFIG_RAMBOOT_SDCARD) #define CONFIG_FSL_FIXED_MMC_LOCATION -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#elif defined(CONFIG_SYS_RAMBOOT) -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -#define CONFIG_ENV_SIZE 0x2000 - -#else -#define CONFIG_ENV_BASE (CONFIG_SYS_FLASH_BASE) -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#define CONFIG_ENV_ADDR (CONFIG_ENV_BASE + 0xC0000) -#if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT) -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE #endif -#endif - -#endif /* CONFIG_ENV_FIT_UCBOOT */ - #define CONFIG_LOADS_ECHO /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ @@ -410,9 +386,7 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ #ifdef CONFIG_MMC -#define CONFIG_FSL_ESDHC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#define CONFIG_MMC_SPI #endif /* Misc Extra Settings */ @@ -450,7 +424,6 @@ #define CONFIG_BOOTP_SERVERIP -#define CONFIG_MII /* MII PHY management */ #define CONFIG_TSEC1_NAME "eTSEC1" #define CONFIG_TSEC2_NAME "eTSEC2" #define CONFIG_TSEC3_NAME "eTSEC3" @@ -470,7 +443,7 @@ #endif -#define CONFIG_HOSTNAME UCP1020 +#define CONFIG_HOSTNAME "UCP1020" #define CONFIG_ROOTPATH "/opt/nfsroot" #define CONFIG_BOOTFILE "uImage" #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */