X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FTQM885D.h;h=7418512a153cda082df7800260b86725c8110117;hb=2ae1824196884ba2bafffb7c0d3e8297350591e9;hp=ede4e3b9b34fe53ec797e9e087a8f9bfa9312ce5;hpb=4a39616da41840bbc5b4c3f69df9861c2e6a8425;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h index ede4e3b..7418512 100644 --- a/include/configs/TQM885D.h +++ b/include/configs/TQM885D.h @@ -39,22 +39,18 @@ #define CONFIG_MPC885 1 /* This is a MPC885 CPU */ #define CONFIG_TQM885D 1 /* ...on a TQM88D module */ +#define CONFIG_SYS_TEXT_BASE 0x40000000 + #define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ -#define CFG_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ -#define CFG_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ -#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 50 MHz - CPU default clock */ +#define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ +#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ +#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 66 MHz - CPU default clock */ /* (it will be used if there is no */ /* 'cpuclk' variable with valid value) */ -#define CFG_MEASURE_CPUCLK /* Measure real cpu clock */ - /* (function measure_gclk() */ - /* will be called) */ -#ifdef CFG_MEASURE_CPUCLK -#define CFG_8XX_XIN 10000000 /* measure_gclk() needs this */ -#endif - #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ - +#define CONFIG_SYS_SMC_RXBUFLEN 128 +#define CONFIG_SYS_MAXIDLE 10 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ #define CONFIG_BOOTCOUNT_LIMIT @@ -64,7 +60,7 @@ #define CONFIG_BOARD_TYPES 1 /* support board types */ #define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS @@ -83,14 +79,20 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM866M/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40180000\0" \ + "bootfile=/tftpboot/TQM885D/uImage\0" \ + "fdt_addr=400C0000\0" \ + "kernel_addr=40100000\0" \ + "ramdisk_addr=40280000\0" \ + "load=tftp 200000 ${u-boot}\0" \ + "update=protect off 40000000 +${filesize};" \ + "erase 40000000 +${filesize};" \ + "cp.b 200000 40000000 ${filesize};" \ + "protect on 40000000 +${filesize}\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ +#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -102,8 +104,8 @@ #undef CONFIG_HARD_I2C /* I2C with hardware support */ #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */ -#define CFG_I2C_SLAVE 0xFE +#define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */ +#define CONFIG_SYS_I2C_SLAVE 0xFE #ifdef CONFIG_SOFT_I2C /* @@ -123,73 +125,83 @@ #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ #endif /* CONFIG_SOFT_I2C */ -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ -#define CFG_EEPROM_PAGE_WRITE_BITS 4 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ # define CONFIG_RTC_DS1337 1 -# define CFG_I2C_RTC_ADDR 0x68 +# define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION -#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */ +#undef CONFIG_RTC_MPC8xx /* MPC885 does not support RTC */ #define CONFIG_TIMESTAMP /* but print image timestmps */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_MII | \ - CFG_CMD_NFS | \ - CFG_CMD_PING ) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING + /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_MEMTEST_START 0x0100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0300000 /* 1 ... 3 MB in DRAM */ -#define CFG_ALT_MEMTEST /* alternate, more extensive +#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x0300000 /* 1 ... 3 MB in DRAM */ +#define CONFIG_SYS_ALT_MEMTEST /* alternate, more extensive memory test.*/ -#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* - * Enable loopw commando. This has only effect, if CFG_CMD_MEM is defined, - * which is normally part of the default commands (CFV_CMD_DFL) + * Enable loopw command. */ #define CONFIG_LOOPW @@ -201,66 +213,70 @@ /*----------------------------------------------------------------------- * Internal Memory Mapped Register */ -#define CFG_IMMR 0xFFF00000 +#define CONFIG_SYS_IMMR 0xFFF00000 /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR +#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_FLASH_BASE 0x40000000 +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */ /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +/* use CFI flash driver */ +#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ +#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ +#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) /*----------------------------------------------------------------------- * Hardware Information Block */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ +#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ +#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ +#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif /*----------------------------------------------------------------------- @@ -270,10 +286,10 @@ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze */ #if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ +#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) #else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) #endif /*----------------------------------------------------------------------- @@ -282,9 +298,9 @@ * PCMCIA config., multi-function pin tri-state */ #ifndef CONFIG_CAN_DRIVER -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) #else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) #endif /* CONFIG_CAN_DRIVER */ /*----------------------------------------------------------------------- @@ -292,14 +308,14 @@ *----------------------------------------------------------------------- * Clear Reference Interrupt Status, Timebase freezing enabled */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) +#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) /*----------------------------------------------------------------------- * PISCR - Periodic Interrupt Status and Control 11-31 *----------------------------------------------------------------------- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) +#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) /*----------------------------------------------------------------------- * SCCR - System Clock and reset Control Register 15-27 @@ -308,7 +324,7 @@ * power management and some other internal clocks */ #define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ +#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ SCCR_DFALCD00) @@ -317,14 +333,14 @@ *----------------------------------------------------------------------- * */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) +#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) +#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) +#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) +#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) /*----------------------------------------------------------------------- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) @@ -337,28 +353,28 @@ #undef CONFIG_IDE_LED /* LED for ide not supported */ #undef CONFIG_IDE_RESET /* reset for ide not supported */ -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ +#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ -#define CFG_ATA_IDE0_OFFSET 0x0000 +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR +#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR /* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) +#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) /* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) +#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) /* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 +#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 /*----------------------------------------------------------------------- * *----------------------------------------------------------------------- * */ -#define CFG_DER 0 +#define CONFIG_SYS_DER 0 /* * Init Memory Controller: @@ -373,22 +389,22 @@ * restrict access enough to keep SRAM working (if any) * but not too much to meddle with FLASH accesses */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ +#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ /* * FLASH timing: Default value of OR0 after reset */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ +#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ OR_SCY_6_CLK | OR_TRLX) -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) +#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) +#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) +#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) +#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM +#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) /* * BR2/3 and OR2/3 (SDRAM) @@ -399,19 +415,19 @@ #define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */ /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 +#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) +#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) +#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) #ifndef CONFIG_CAN_DRIVER -#define CFG_OR3_PRELIM CFG_OR2_PRELIM -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) +#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM +#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) -#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ +#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ +#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ +#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) +#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ BR_PS_8 | BR_MS_UPMB | BR_V ) #endif /* CONFIG_CAN_DRIVER */ @@ -422,44 +438,48 @@ * 4 Number of refresh cycles per period * 64 Refresh cycle in ms per number of rows */ -#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) +#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) /* - * Memory Periodic Timer Prescaler - * Periodic timer for refresh, start with refresh rate for 40 MHz clock - * (CFG_8xx_CPUCLK_MIN / CFG_PTA_PER_CLK) + * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad) + * + * CPUclock(MHz) * 31.2 + * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0 + * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16 + * + * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us + * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us + * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us + * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us + * + * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will + * be met also in the default configuration, i.e. if environment variable + * 'cpuclk' is not set. */ -#define CFG_MAMR_PTA 39 +#define CONFIG_SYS_MAMR_PTA 128 /* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank + * Memory Periodic Timer Prescaler Register (MPTPR) values. */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ +/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */ +#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 +/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */ +#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* * MAMR settings for SDRAM */ /* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ +#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) /* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ +#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) /* 10 column SDRAM */ -#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ +#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) @@ -479,14 +499,20 @@ #define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */ #define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */ -#if (CONFIG_COMMANDS & CFG_CMD_MII) -#define CFG_DISCOVER_PHY +#if defined(CONFIG_CMD_MII) +#define CONFIG_SYS_DISCOVER_PHY +#define CONFIG_MII_INIT 1 #endif #define CONFIG_NET_RETRY_COUNT 1 /* reduce max. timeout before switching to another netwok (if the tried network is unreachable) */ -#define CONFIG_ETHPRIME "SCC ETHERNET" +#define CONFIG_ETHPRIME "SCC" + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_HWCONFIG 1 #endif /* __CONFIG_H */