X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FTQM862L.h;h=6c610ee5904a8493658efbc797f53057b47a54bc;hb=28ac6719108e989429de2b3dfa90312ba7c4d27b;hp=23e7d1f05bd589393dc6f9d8ce83a7c55b8afc8d;hpb=ae3af05ec986a8ac66dadb5eafe13db2d4a02c5c;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h
index 23e7d1f..6c610ee 100644
--- a/include/configs/TQM862L.h
+++ b/include/configs/TQM862L.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2003
+ * (C) Copyright 2000-2008
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -52,7 +52,7 @@
 #define CONFIG_BOARD_TYPES	1	/* support board types		*/
 
 #define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 	"echo"
 
 #undef	CONFIG_BOOTARGS
@@ -60,20 +60,28 @@
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 	"netdev=eth0\0"							\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=$(serverip):$(rootpath)\0"			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs $(bootargs) "				\
-		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
-		":$(hostname):$(netdev):off panic=1\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
 	"flash_nfs=run nfsargs addip;"					\
-		"bootm $(kernel_addr)\0"				\
+		"bootm ${kernel_addr}\0"				\
 	"flash_self=run ramargs addip;"					\
-		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
-	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
 	"rootpath=/opt/eldk/ppc_8xx\0"					\
-	"bootfile=/tftpboot/TQM860L/uImage\0"				\
-	"kernel_addr=40040000\0"					\
-	"ramdisk_addr=40100000\0"					\
+	"hostname=TQM862L\0"						\
+	"bootfile=TQM862L/uImage\0"					\
+	"fdt_addr=40040000\0"						\
+	"kernel_addr=40060000\0"					\
+	"ramdisk_addr=40200000\0"					\
+	"u-boot=TQM862L/u-image.bin\0"					\
+	"load=tftp 200000 ${u-boot}\0"					\
+	"update=prot off 40000000 +${filesize};"			\
+		"era 40000000 +${filesize};"				\
+		"cp.b 200000 40000000 ${filesize};"			\
+		"sete filesize;save\0"					\
 	""
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
@@ -86,21 +94,39 @@
 
 #undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
 
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
 
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
 
 #define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
 
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_ASKENV	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_IDE	| \
-				CFG_CMD_DATE	)
 
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+
+#define CONFIG_NETCONSOLE
+
 
 /*
  * Miscellaneous configurable options
@@ -108,14 +134,13 @@
 #define	CFG_LONGHELP			/* undef to save memory		*/
 #define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
-#if 0
-#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
-#endif
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
 #ifdef	CFG_HUSH_PARSER
 #define	CFG_PROMPT_HUSH_PS2	"> "
 #endif
 
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 #define	CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
 #else
 #define	CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
@@ -173,14 +198,17 @@
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+/* use CFI flash driver */
+#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
+#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_USE_BUFFER_WRITE	1
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
 
 #define	CFG_ENV_IS_IN_FLASH	1
-
 #define	CFG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
 #define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
 
@@ -188,6 +216,20 @@
 #define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SIZE)
 #define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
 
+#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+
+/*-----------------------------------------------------------------------
+ * Dynamic MTD partition support
+ */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=TQM8xxL-0"
+
+#define MTDPARTS_DEFAULT	"mtdparts=TQM8xxL-0:256k(u-boot),"	\
+						"128k(dtb),"		\
+						"1664k(kernel),"	\
+						"2m(rootfs),"		\
+						"4m(data)"
+
 /*-----------------------------------------------------------------------
  * Hardware Information Block
  */
@@ -199,7 +241,7 @@
  * Cache Configuration
  */
 #define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
@@ -252,16 +294,8 @@
  *-----------------------------------------------------------------------
  * Reset PLL lock status sticky bit, timer expired status bit and timer
  * interrupt status bit
- *
- * If this is a 80 MHz or 100 MHz CPU,
- * set PLL multiplication factor to 5 (5 * 16 = 80, 5 * 20 = 100)
  */
-#if defined(CONFIG_80MHz) || defined(CONFIG_100MHz)
-#define CFG_PLPRCR							\
-		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
-#else			/* up to 66 MHz we use a 1:1 clock */
 #define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-#endif	/* CONFIG_80MHz | CONFIG_100MHz */
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -270,17 +304,9 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#if defined(CONFIG_80MHz) || defined(CONFIG_100MHz) /* use 16/20 MHz * 5 */
-#define CFG_SCCR	(/* SCCR_TBS  | */ \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
-#else			/* up to 66 MHz we use a 1:1 clock */
-#define CFG_SCCR	(SCCR_TBS     | \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00)
-#endif	/* CONFIG_80MHz | CONFIG_100MHz */
 
 /*-----------------------------------------------------------------------
  * PCMCIA stuff
@@ -349,24 +375,8 @@
 /*
  * FLASH timing:
  */
-#if defined(CONFIG_100MHz)
-/* 100 MHz CPU - 50 MHz bus:
- * ACS = 01, TRLX = 0, CSNT = 0, SCY = 7, EHTR = 0 */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV4  | OR_SCY_7_CLK | OR_BI)
-#elif defined(CONFIG_80MHz)
-/* 80 MHz CPU - 40 MHz bus:
- * ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | 0       | OR_CSNT_SAM | \
-				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
-#elif defined(CONFIG_66MHz)
-/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
 #define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
-#else		/*   50 MHz */
-/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
-				 OR_SCY_2_CLK | OR_EHTR | OR_BI)
-#endif	/*CONFIG_??MHz */
 
 #define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 #define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
@@ -428,15 +438,9 @@
  *  80 Mhz =>  80.000.000 / Divider = 156
  * 100 Mhz => 100.000.000 / Divider = 195
  */
-#if   defined(CONFIG_100MHz)
-#define CFG_MAMR_PTA		195
-#elif defined(CONFIG_80MHz)
-#define CFG_MAMR_PTA		156
-#elif defined(CONFIG_66MHz)
-#define CFG_MAMR_PTA		129
-#else		/*   50 MHz */
-#define CFG_MAMR_PTA		 98
-#endif	/*CONFIG_??MHz */
+
+#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CFG_MAMR_PTA	98
 
 /*
  * For 16 MBit, refresh rates could be 31.3 us