X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FTQM834x.h;h=aa70f01dddedb49823dd8ee759ac203260665b4b;hb=2493ce6258a59881b702cbe255db9e53f1e3fd13;hp=c27a04ace996426197c463724abd06c81b21d5e9;hpb=93de25308dac01dd1a6ff5891e13ea849041a88a;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index c27a04a..aa70f01 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -16,21 +16,6 @@ */ #define CONFIG_E300 1 /* E300 Family */ -/* IMMR Base Address Register, use Freescale default: 0xff400000 */ -#define CONFIG_SYS_IMMR 0xff400000 - -/* - * Local Bus LCRR - * LCRR: DLL bypass, Clock divider is 8 - * - * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz - * - * External Local Bus rate is - * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV - */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 - /* board pre init: do not call, nothing to do */ /* detect the number of flash banks */ @@ -39,16 +24,12 @@ * DDR Setup */ /* DDR is system memory*/ -#define CONFIG_SYS_DDR_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 #define DDR_CASLAT_25 /* CASLAT set to 2.5 */ #undef CONFIG_DDR_ECC /* only for ECC DDR module */ #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */ #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00100000 /* * FLASH on the Local Bus @@ -76,43 +57,16 @@ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */ -/* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) \ - | BR_MS_GPCM \ - | BR_PS_32 \ - | BR_V) - -/* FLASH timing (0x0000_0c54) */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV4 \ - | OR_GPCM_SCY_5 \ - | OR_GPCM_TRLX) - -#define CONFIG_SYS_PRELIM_OR_AM OR_AM_1GB /* OR addr mask: 1 GiB */ - -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \ - | CONFIG_SYS_OR_TIMING_FLASH) - -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_1GB) - - /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* disable remaining mappings */ #define CONFIG_SYS_BR1_PRELIM 0x00000000 #define CONFIG_SYS_OR1_PRELIM 0x00000000 -#define CONFIG_SYS_LBLAWBAR1_PRELIM 0x00000000 -#define CONFIG_SYS_LBLAWAR1_PRELIM 0x00000000 #define CONFIG_SYS_BR2_PRELIM 0x00000000 #define CONFIG_SYS_OR2_PRELIM 0x00000000 -#define CONFIG_SYS_LBLAWBAR2_PRELIM 0x00000000 -#define CONFIG_SYS_LBLAWAR2_PRELIM 0x00000000 #define CONFIG_SYS_BR3_PRELIM 0x00000000 #define CONFIG_SYS_OR3_PRELIM 0x00000000 -#define CONFIG_SYS_LBLAWBAR3_PRELIM 0x00000000 -#define CONFIG_SYS_LBLAWAR3_PRELIM 0x00000000 /* * Monitor config @@ -213,9 +167,6 @@ #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ -#undef CONFIG_EEPRO100 -#define CONFIG_EEPRO100 -#undef CONFIG_TULIP #if !defined(CONFIG_PCI_PNP) #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE @@ -230,12 +181,6 @@ /* * Environment */ -#define CONFIG_ENV_ADDR \ - (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */ -#define CONFIG_ENV_SIZE 0x8000 /* 32K max size */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ @@ -264,109 +209,11 @@ #define CONFIG_SYS_SICRH 0 #define CONFIG_SYS_SICRL SICRL_LDP_A -/* i-cache and d-cache disabled */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - -/* DDR 0 - 512M */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* stack in DCACHE @ 512M (no backing mem) */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR \ - | BATU_BL_128K \ - | BATU_VS \ - | BATU_VP) - /* PCI */ #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE \ - | BATU_BL_16M \ - | BATU_VS \ - | BATU_VP) -#else -#define CONFIG_SYS_IBAT3L (0) -#define CONFIG_SYS_IBAT3U (0) -#define CONFIG_SYS_IBAT4L (0) -#define CONFIG_SYS_IBAT4U (0) -#define CONFIG_SYS_IBAT5L (0) -#define CONFIG_SYS_IBAT5U (0) #endif -/* IMMRBAR */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR \ - | BATU_BL_1M \ - | BATU_VS \ - | BATU_VP) - -/* FLASH */ -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif @@ -378,10 +225,6 @@ /* default location for tftp and bootm */ #define CONFIG_LOADADDR 400000 -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "hostname=tqm834x\0" \