X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FTQM834x.h;h=0da34d05afcb4d603f9dc6d8cf0f000e307740c1;hb=56730706cc6842e852fb6d2c6fd90d07786c2ecf;hp=c5a6203001b72aecbfa3c4f01f26ca58998ec0de;hpb=30915ab95d9a95328623010390d94da1325529f9;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index c5a6203..0da34d0 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -16,21 +16,6 @@
  */
 #define CONFIG_E300		1	/* E300 Family */
 
-/* IMMR Base Address Register, use Freescale default: 0xff400000 */
-#define CONFIG_SYS_IMMR		0xff400000
-
-/*
- * Local Bus LCRR
- *    LCRR:  DLL bypass, Clock divider is 8
- *
- *    for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
- *
- * External Local Bus rate is
- *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
- */
-#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_8
-
 /* board pre init: do not call, nothing to do */
 
 /* detect the number of flash banks */
@@ -39,9 +24,7 @@
  * DDR Setup
  */
 				/* DDR is system memory*/
-#define CONFIG_SYS_DDR_BASE	0x00000000
-#define CONFIG_SYS_SDRAM_BASE	CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE	0x00000000
 #define DDR_CASLAT_25		/* CASLAT set to 2.5 */
 #undef CONFIG_DDR_ECC		/* only for ECC DDR module */
 #undef CONFIG_SPD_EEPROM	/* do not use SPD EEPROM for DDR setup */
@@ -76,43 +59,16 @@
 
 #define CONFIG_SYS_MAX_FLASH_SECT	512	/* max sectors per device */
 
-/* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
-#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_FLASH_BASE & BR_BA) \
-				| BR_MS_GPCM \
-				| BR_PS_32 \
-				| BR_V)
-
-/* FLASH timing (0x0000_0c54) */
-#define CONFIG_SYS_OR_TIMING_FLASH	(OR_GPCM_CSNT \
-					| OR_GPCM_ACS_DIV4 \
-					| OR_GPCM_SCY_5 \
-					| OR_GPCM_TRLX)
-
-#define CONFIG_SYS_PRELIM_OR_AM		OR_AM_1GB /* OR addr mask: 1 GiB */
-
-#define CONFIG_SYS_OR0_PRELIM		(CONFIG_SYS_PRELIM_OR_AM  \
-					| CONFIG_SYS_OR_TIMING_FLASH)
-
-#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_1GB)
-
-					/* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
 
 /* disable remaining mappings */
 #define CONFIG_SYS_BR1_PRELIM		0x00000000
 #define CONFIG_SYS_OR1_PRELIM		0x00000000
-#define CONFIG_SYS_LBLAWBAR1_PRELIM	0x00000000
-#define CONFIG_SYS_LBLAWAR1_PRELIM	0x00000000
 
 #define CONFIG_SYS_BR2_PRELIM		0x00000000
 #define CONFIG_SYS_OR2_PRELIM		0x00000000
-#define CONFIG_SYS_LBLAWBAR2_PRELIM	0x00000000
-#define CONFIG_SYS_LBLAWAR2_PRELIM	0x00000000
 
 #define CONFIG_SYS_BR3_PRELIM		0x00000000
 #define CONFIG_SYS_OR3_PRELIM		0x00000000
-#define CONFIG_SYS_LBLAWBAR3_PRELIM	0x00000000
-#define CONFIG_SYS_LBLAWAR3_PRELIM	0x00000000
 
 /*
  * Monitor config
@@ -264,12 +220,6 @@
 #define CONFIG_SYS_SICRH	0
 #define CONFIG_SYS_SICRL	SICRL_LDP_A
 
-/* i-cache and d-cache disabled */
-#define CONFIG_SYS_HID0_INIT	0x000000000
-#define CONFIG_SYS_HID0_FINAL	(CONFIG_SYS_HID0_INIT | \
-				 HID0_ENABLE_INSTRUCTION_CACHE)
-#define CONFIG_SYS_HID2	HID2_HBE
-
 /* PCI */
 #ifdef CONFIG_PCI
 #define CONFIG_PCI_INDIRECT_BRIDGE