X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FTQM8260.h;h=3b7832397f247cf1bf037b80d475a21f91a4fabf;hb=bb701283a8dcb2521000fe437f19a83cadc98b02;hp=86281dd5fbed136cc08a284468110d6435440f60;hpb=4532cb696eb717419022dbaa8d408e7df7df7b68;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/TQM8260.h b/include/configs/TQM8260.h index 86281dd..3b78323 100644 --- a/include/configs/TQM8260.h +++ b/include/configs/TQM8260.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2001 + * (C) Copyright 2001-2005 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -30,10 +30,13 @@ /* * Imported from global configuration: - * CONFIG_L2_CACHE + * CONFIG_MPC8255 + * CONFIG_MPC8265 + * CONFIG_200MHz * CONFIG_266MHz * CONFIG_300MHz - * CONFIG_MPC8255 + * CONFIG_L2_CACHE + * CONFIG_BUSMODE_60x */ /* @@ -49,40 +52,37 @@ #define CONFIG_TQM8260 200 /* ...on a TQM8260 module Rev.200 */ #endif -/* Define 60x busmode only if your TQM8260 has L2 cache! */ -#ifdef CONFIG_L2_CACHE -# define CONFIG_BUSMODE_60x 1 /* bus mode: 60x */ -#else -# undef CONFIG_BUSMODE_60x /* bus mode: 8260 */ -#endif - -/* The board with 300MHz CPU doesn't have L2 cache, but works in 60x bus mode */ -#ifdef CONFIG_300MHz -# define CONFIG_BUSMODE_60x -#endif +#define CONFIG_CPM2 1 /* Has a CPM2 */ #define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ +#define CONFIG_BOOTCOUNT_LIMIT + +#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) +#define CONFIG_BAUDRATE 230400 +#else +#define CONFIG_BAUDRATE 9600 +#endif #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" #undef CONFIG_BOOTARGS #define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ "flash_nfs=run nfsargs addip;" \ - "bootm $(kernel_addr)\0" \ + "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_82xx\0" \ "bootfile=/tftpboot/TQM8260/uImage\0" \ "kernel_addr=40040000\0" \ @@ -167,8 +167,7 @@ * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. + * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. * * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the * X.29 connector, and FCC2 is hardwired to the X.1 connector) @@ -203,38 +202,59 @@ /* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#ifndef CONFIG_300MHz -#define CONFIG_8260_CLKIN 66666666 /* in Hz */ -#else -#define CONFIG_8260_CLKIN 83333000 /* in Hz */ -#endif - -#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) -#define CONFIG_BAUDRATE 230400 -#else -#define CONFIG_BAUDRATE 9600 -#endif +#if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265) +# define CONFIG_8260_CLKIN 66666666 /* in Hz */ +#else /* !CONFIG_MPC8255 && !CONFIG_MPC8265 */ +# ifndef CONFIG_300MHz +# define CONFIG_8260_CLKIN 66666666 /* in Hz */ +# else +# define CONFIG_8260_CLKIN 83333000 /* in Hz */ +# endif +#endif /* CONFIG_MPC8255 */ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ #undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_I2C | \ - CFG_CMD_EEPROM) +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -311,15 +331,19 @@ * defines for the various registers affected by the HRCW e.g. changing * HRCW_DPPCxx requires you to also change CFG_SIUMCR. */ -#if defined(CONFIG_266MHz) -#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \ - HRCW_MODCK_H0111) -#elif defined(CONFIG_300MHz) -#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \ - HRCW_MODCK_H0110) -#else -#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS) -#endif +#define __HRCW__ALL__ (HRCW_CIP | HRCW_ISB111 | HRCW_BMS) + +#if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265) +# define CFG_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111) +#else /* ! MPC8255 && !MPC8265 */ +# if defined(CONFIG_266MHz) +# define CFG_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111) +# elif defined(CONFIG_300MHz) +# define CFG_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0110) +# else +# define CFG_HRCW_MASTER (__HRCW__ALL__) +# endif +#endif /* CONFIG_MPC8255 */ /* no slaves so just fill with zeros */ #define CFG_HRCW_SLAVE1 0 @@ -371,7 +395,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -386,7 +410,7 @@ * HID1 has only read-only information - nothing to set. */ #define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ - HID0_IFEM|HID0_ABE) + HID0_IFEM|HID0_ABE) #define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) #define CFG_HID2 0 @@ -428,10 +452,10 @@ */ #if defined(CONFIG_WATCHDOG) #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) + SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) #else #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) + SYPCR_SWRI|SYPCR_SWP) #endif /* CONFIG_WATCHDOG */ /*----------------------------------------------------------------------- @@ -509,16 +533,16 @@ /* Bank 0 - FLASH */ #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_GPCM_P |\ - BRx_V) + BRx_PS_64 |\ + BRx_MS_GPCM_P |\ + BRx_V) #define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxG_EHTR |\ - ORxG_TRLX) + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_3_CLK |\ + ORxG_EHTR |\ + ORxG_TRLX) /* SDRAM on TQM8260 can have either 8 or 9 columns. * The number affects configuration values. @@ -530,9 +554,9 @@ #define CFG_LSRT 0x20 #ifndef CFG_RAMBOOT #define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) + BRx_PS_64 |\ + BRx_MS_SDRAM_P |\ + BRx_V) #define CFG_OR1_PRELIM CFG_OR1_8COL @@ -540,48 +564,48 @@ /* SDRAM initialization values for 8-column chips */ #define CFG_OR1_8COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A7 |\ - ORxS_NUMR_12) + ORxS_BPD_4 |\ + ORxS_ROWST_PBI1_A7 |\ + ORxS_NUMR_12) #define CFG_PSDMR_8COL (PSDMR_PBI |\ - PSDMR_SDAM_A15_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A8 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_CL_2) + PSDMR_SDAM_A15_IS_A5 |\ + PSDMR_BSMA_A12_A14 |\ + PSDMR_SDA10_PBI1_A8 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_2C |\ + PSDMR_EAMUX |\ + PSDMR_CL_2) /* SDRAM initialization values for 9-column chips */ #define CFG_OR1_9COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A5 |\ - ORxS_NUMR_13) + ORxS_BPD_4 |\ + ORxS_ROWST_PBI1_A5 |\ + ORxS_NUMR_13) #define CFG_PSDMR_9COL (PSDMR_PBI |\ - PSDMR_SDAM_A16_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A7 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_CL_2) + PSDMR_SDAM_A16_IS_A5 |\ + PSDMR_BSMA_A12_A14 |\ + PSDMR_SDA10_PBI1_A7 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_2C |\ + PSDMR_EAMUX |\ + PSDMR_CL_2) /* Bank 2 - Local bus SDRAM */ #ifdef CFG_INIT_LOCAL_SDRAM #define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_SDRAM_L |\ - BRx_V) + BRx_PS_32 |\ + BRx_MS_SDRAM_L |\ + BRx_V) #define CFG_OR2_PRELIM CFG_OR2_8COL @@ -590,40 +614,40 @@ /* SDRAM initialization values for 8-column chips */ #define CFG_OR2_8COL ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A8 |\ - ORxS_NUMR_12) + ORxS_BPD_4 |\ + ORxS_ROWST_PBI1_A8 |\ + ORxS_NUMR_12) #define CFG_LSDMR_8COL (PSDMR_PBI |\ - PSDMR_SDAM_A15_IS_A5 |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_SDA10_PBI1_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_BL |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_CL_2) + PSDMR_SDAM_A15_IS_A5 |\ + PSDMR_BSMA_A13_A15 |\ + PSDMR_SDA10_PBI1_A9 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_BL |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_2C |\ + PSDMR_CL_2) /* SDRAM initialization values for 9-column chips */ #define CFG_OR2_9COL ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A6 |\ - ORxS_NUMR_13) + ORxS_BPD_4 |\ + ORxS_ROWST_PBI1_A6 |\ + ORxS_NUMR_13) #define CFG_LSDMR_9COL (PSDMR_PBI |\ - PSDMR_SDAM_A16_IS_A5 |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_SDA10_PBI1_A8 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_BL |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_CL_2) + PSDMR_SDAM_A16_IS_A5 |\ + PSDMR_BSMA_A13_A15 |\ + PSDMR_SDA10_PBI1_A8 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_BL |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_2C |\ + PSDMR_CL_2) #endif /* CFG_INIT_LOCAL_SDRAM */