X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FT208xQDS.h;h=c54f7f53e575eaae6c5c674247128494c7cece3d;hb=1af3c7f422f627a544fec13e436d1a7975e39e73;hp=f09a9ddf3b4f2b92738c8f04b50cf4d5041ddd37;hpb=2b12f6cfe6239d8b6b8c5e7b0c5b5851f7bc489a;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index f09a9dd..c54f7f5 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2011-2013 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ /* @@ -10,6 +11,8 @@ #ifndef __T208xQDS_H #define __T208xQDS_H +#include + #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ #if defined(CONFIG_ARCH_T2080) #define CONFIG_FSL_SATA_V2 @@ -46,7 +49,7 @@ #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE #endif -#ifdef CONFIG_NAND +#ifdef CONFIG_MTD_RAW_NAND #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 @@ -118,25 +121,8 @@ #endif #if defined(CONFIG_SPIFLASH) -#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ -#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ -#define CONFIG_ENV_SECT_SIZE 0x10000 #elif defined(CONFIG_SDCARD) #define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (512 * 0x800) -#elif defined(CONFIG_NAND) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) -#define CONFIG_ENV_ADDR 0xffe20000 -#define CONFIG_ENV_SIZE 0x2000 -#elif defined(CONFIG_ENV_IS_NOWHERE) -#define CONFIG_ENV_SIZE 0x2000 -#else -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif #ifndef __ASSEMBLY__ @@ -153,9 +139,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 #define CONFIG_SYS_L3_SIZE (512 << 10) #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) -#endif +#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) @@ -307,7 +291,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) -#if defined(CONFIG_NAND) +#if defined(CONFIG_MTD_RAW_NAND) #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK @@ -404,8 +388,8 @@ unsigned long get_board_ddr_clk(void); /* * I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F @@ -418,6 +402,10 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_FSL_I2C2_SPEED 100000 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 +#endif + +#define CONFIG_SYS_I2C_FSL + #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ @@ -491,49 +479,51 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_PCIE4 /* PCIE controller 4 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* controller 4, Base address 203000 */ #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ #ifdef CONFIG_PCI +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ #define CONFIG_PCI_INDIRECT_BRIDGE +#endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif @@ -585,7 +575,7 @@ unsigned long get_board_ddr_clk(void); * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. */ #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) -#elif defined(CONFIG_NAND) +#elif defined(CONFIG_MTD_RAW_NAND) #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* @@ -604,9 +594,6 @@ unsigned long get_board_ddr_clk(void); #endif /* CONFIG_NOBQFMAN */ #ifdef CONFIG_SYS_DPAA_FMAN -#define CONFIG_PHY_VITESSE -#define CONFIG_PHY_REALTEK -#define CONFIG_PHY_TERANETICS #define RGMII_PHY1_ADDR 0x1 #define RGMII_PHY2_ADDR 0x2 #define FM1_10GEC1_PHY_ADDR 0x3 @@ -647,7 +634,6 @@ unsigned long get_board_ddr_clk(void); * SDHC */ #ifdef CONFIG_MMC -#define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33