X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FPPChameleonEVB.h;h=27a12b310be991aa189d057d247b7f39ee7eda89;hb=412665b46134f93464c09405e02f08ac9c62526d;hp=09a96417f5165a8351461c530b64fa9486799e71;hpb=cb5473205206c7f14cbb1e747f28ec75b48826e2;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index 09a9641..27a12b3 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -75,6 +75,9 @@ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */ +#define CONFIG_SYS_TEXT_BASE 0xFFFB0000 /* Reserve 320 kB for Monitor */ +#define CONFIG_SYS_LDSCRIPT "board/dave/PPChameleonEVB/u-boot.lds" + #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ @@ -102,7 +105,6 @@ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ #undef CONFIG_EXT_PHY -#define CONFIG_NET_MULTI 1 #define CONFIG_PPC4xx_EMAC #define CONFIG_MII 1 /* MII PHY management */ @@ -171,9 +173,6 @@ #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#endif #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -191,8 +190,13 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 /* The following table includes the supported baudrates */ @@ -211,6 +215,7 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ + /* * nand device 1 on dave (PPChameleonEVB) needs more time, * so we just introduce additional wait in nand_wait(), @@ -224,8 +229,6 @@ #define NAND_BIG_DELAY_US 25 #define CONFIG_SYS_MAX_NAND_DEVICE 2 /* Max number of NAND devices */ -#define NAND_MAX_CHIPS 1 - #define CONFIG_SYS_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */ #define CONFIG_SYS_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ #define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ @@ -312,32 +315,6 @@ } \ } while(0) -#if 0 -#define SECTORSIZE 512 -#define NAND_NO_RB - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 - -#ifdef NAND_NO_RB -/* constant delay (see also tR in the datasheet) */ -#define NAND_WAIT_READY(nand) do { \ - udelay(12); \ -} while (0) -#else -/* use the R/B pin */ -/* TBD */ -#endif - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) -#endif /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- @@ -442,6 +419,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F @@ -550,10 +528,9 @@ #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */ +#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /*----------------------------------------------------------------------- @@ -569,24 +546,15 @@ * GPIO0[30] - EMAC0 input * GPIO0[31] - EMAC1 reject packet as output */ -#define CONFIG_SYS_GPIO0_OSRH 0x40000550 -#define CONFIG_SYS_GPIO0_OSRL 0x00000110 -#define CONFIG_SYS_GPIO0_ISR1H 0x00000000 -/*#define CONFIG_SYS_GPIO0_ISR1L 0x15555445*/ -#define CONFIG_SYS_GPIO0_ISR1L 0x15555444 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 +#define CONFIG_SYS_GPIO0_OSRL 0x40000550 +#define CONFIG_SYS_GPIO0_OSRH 0x00000110 +#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 +/*#define CONFIG_SYS_GPIO0_ISR1H 0x15555445*/ +#define CONFIG_SYS_GPIO0_ISR1H 0x15555444 #define CONFIG_SYS_GPIO0_TSRL 0x00000000 +#define CONFIG_SYS_GPIO0_TSRH 0x00000000 #define CONFIG_SYS_GPIO0_TCR 0xF7FF8014 -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - #define CONFIG_NO_SERIAL_EEPROM /*--------------------------------------------------------------------*/ @@ -604,17 +572,6 @@ #define DIMM_READ_ADDR 0xAB #define DIMM_WRITE_ADDR 0xAA -#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ -#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ -#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ -#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register */ -#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */ -#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */ -#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */ -#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */ -#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */ -#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */ - /* Defines for CPC0_PLLMR1 Register fields */ #define PLL_ACTIVE 0x80000000 #define CPC0_PLLMR1_SSCS 0x80000000 @@ -807,14 +764,14 @@ */ /* No command line, one static partition */ -#undef CONFIG_JFFS2_CMDLINE +#undef CONFIG_CMD_MTDPARTS #define CONFIG_JFFS2_DEV "nand0" #define CONFIG_JFFS2_PART_SIZE 0x00400000 #define CONFIG_JFFS2_PART_OFFSET 0x00000000 /* mtdparts command line support */ /* -#define CONFIG_JFFS2_CMDLINE +#define CONFIG_CMD_MTDPARTS #define MTDIDS_DEFAULT "nor0=PPChameleon-0,nand0=ppchameleonevb-nand" */