X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FPN62.h;h=2c0774fea03ee6606834f161dbf252161a9a2e77;hb=c1b7c70083fc8d0bb77db20dd47bb6c988f3dc67;hp=5f748a0366e0357e07d173b21afd18eaf4c146d9;hpb=e2ffd59b4d93c9149de1caaa087371b0cfc512c9;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/PN62.h b/include/configs/PN62.h index 5f748a0..2c0774f 100644 --- a/include/configs/PN62.h +++ b/include/configs/PN62.h @@ -42,15 +42,29 @@ #define CONFIG_CONS_INDEX 1 -#define REMOVE_COMMANDS ( CFG_CMD_AUTOSCRIPT | \ - CFG_CMD_LOADS | \ - CFG_CMD_ENV | \ - CFG_CMD_FLASH | \ - CFG_CMD_IMLS ) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PCI +#define CONFIG_CMD_BSP + +#undef CONFIG_CMD_AUTOSCRIPT +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_ENV +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_IMLS -#define CONFIG_COMMANDS ( (CONFIG_CMD_DFL & ~REMOVE_COMMANDS) |\ - CFG_CMD_PCI |\ - CFG_CMD_BSP) #define CONFIG_BAUDRATE 19200 /* console baudrate */ @@ -59,7 +73,7 @@ #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ #define CONFIG_SERVERIP 10.0.0.201 -#define CONFIG_IPADDR 10.0.0.200 +#define CONFIG_IPADDR 10.0.0.200 #define CONFIG_ROOTPATH /opt/eldk/ppc_82xx #define CONFIG_NETMASK 255.255.255.0 #undef CONFIG_BOOTARGS @@ -67,36 +81,32 @@ /* Boot Linux with NFS root filesystem */ #define CONFIG_BOOTCOMMAND \ "setenv verify y;" \ - "setenv bootargs console=ttyS0,19200 mem=31M quiet " \ - "root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip)::$(netmask):pn62:eth0:off;" \ + "setenv bootargs console=ttyS0,19200 mem=31M quiet " \ + "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \ "loadp 100000; bootm" /* "tftpboot 100000 uImage; bootm" */ #else /* Boot Linux with RAMdisk based filesystem (initrd, BusyBox) */ #define CONFIG_BOOTCOMMAND \ "setenv verify n;" \ - "setenv bootargs console=ttyS0,19200 mem=31M quiet " \ + "setenv bootargs console=ttyS0,19200 mem=31M quiet " \ "root=/dev/ram rw " \ - "ip=$(ipaddr):$(serverip)::$(netmask):pn62:eth0:off;" \ + "ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \ "loadp 200000; bootm" #endif -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - - /* * Miscellaneous configurable options */ -#define CFG_LONGHELP 1 /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x00100000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ #define CONFIG_PRAM 1024 /* reserve 1 MB protected RAM */ @@ -118,7 +128,7 @@ /* * Networking stuff */ -#define CONFIG_NET_MULTI /* Multi ethernet cards support */ +#define CONFIG_NET_MULTI /* Multi ethernet cards support */ #define CONFIG_PCNET /* there are 2 AMD PCnet 79C973 */ #define CONFIG_PCNET_79C973 @@ -129,50 +139,50 @@ /* * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_MAX_RAM_SIZE 0x10000000 +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 -#define CFG_RESET_ADDRESS 0xfff00100 +#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 -#undef CFG_RAMBOOT -#define CFG_MONITOR_LEN 0x00030000 -#define CFG_MONITOR_BASE TEXT_BASE +#undef CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_MONITOR_LEN 0x00030000 +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -/*#define CFG_GBL_DATA_SIZE 256*/ -#define CFG_GBL_DATA_SIZE 128 +/*#define CONFIG_SYS_GBL_DATA_SIZE 256*/ +#define CONFIG_SYS_GBL_DATA_SIZE 128 -#define CFG_INIT_RAM_ADDR 0x40000000 -#define CFG_INIT_RAM_END 0x1000 -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_END 0x1000 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) -#define CFG_NO_FLASH 1 /* There is no FLASH memory */ +#define CONFIG_SYS_NO_FLASH 1 /* There is no FLASH memory */ -#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ -#define CFG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */ +#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ +#define CONFIG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */ +#define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */ -#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ +#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ -#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ -#define CFG_MEMTEST_END 0x01f00000 /* 0 ... 32 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x01f00000 /* 0 ... 32 MB in DRAM */ /* * Serial port configuration */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CFG_NS16550 -#define CFG_NS16550_SERIAL +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK 1843200 +#define CONFIG_SYS_NS16550_CLK 1843200 -#define CFG_NS16550_COM1 0xff800008 -#define CFG_NS16550_COM2 0xff800000 +#define CONFIG_SYS_NS16550_COM1 0xff800008 +#define CONFIG_SYS_NS16550_COM2 0xff800000 /* * Low Level Configuration Settings @@ -183,30 +193,30 @@ #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ #define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3 -#define CFG_EUMB_ADDR 0xFCE00000 +#define CONFIG_SYS_EUMB_ADDR 0xFCE00000 /* MCCR1 */ -#define CFG_ROMNAL 3 /* rom/flash next access time */ -#define CFG_ROMFAL 7 /* rom/flash access time */ +#define CONFIG_SYS_ROMNAL 3 /* rom/flash next access time */ +#define CONFIG_SYS_ROMFAL 7 /* rom/flash access time */ /* MCCR2 */ -#define CFG_ASRISE 6 /* ASRISE in clocks */ -#define CFG_ASFALL 12 /* ASFALL in clocks */ -#define CFG_REFINT 5600 /* REFINT in clocks */ +#define CONFIG_SYS_ASRISE 6 /* ASRISE in clocks */ +#define CONFIG_SYS_ASFALL 12 /* ASFALL in clocks */ +#define CONFIG_SYS_REFINT 5600 /* REFINT in clocks */ /* MCCR3 */ -#define CFG_BSTOPRE 0x3cf /* Burst To Precharge */ -#define CFG_REFREC 2 /* Refresh to activate interval */ -#define CFG_RDLAT 3 /* data latency from read command */ +#define CONFIG_SYS_BSTOPRE 0x3cf /* Burst To Precharge */ +#define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */ +#define CONFIG_SYS_RDLAT 3 /* data latency from read command */ /* MCCR4 */ -#define CFG_PRETOACT 1 /* Precharge to activate interval */ -#define CFG_ACTTOPRE 3 /* Activate to Precharge interval */ -#define CFG_ACTORW 2 /* Activate to R/W */ -#define CFG_SDMODE_CAS_LAT 2 /* SDMODE CAS latency */ -#define CFG_SDMODE_WRAP 0 /* SDMODE Wrap type */ -#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */ -#define CFG_REGISTERD_TYPE_BUFFER 1 +#define CONFIG_SYS_PRETOACT 1 /* Precharge to activate interval */ +#define CONFIG_SYS_ACTTOPRE 3 /* Activate to Precharge interval */ +#define CONFIG_SYS_ACTORW 2 /* Activate to R/W */ +#define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latency */ +#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE Wrap type */ +#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */ +#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 /* Memory bank settings: * @@ -215,80 +225,80 @@ * bits will be set to 0x00000 for a start address, or 0xfffff for an * end address */ -#define CFG_BANK0_START 0x00000000 -#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) -#define CFG_BANK0_ENABLE 1 -#define CFG_BANK1_START 0x00000000 -#define CFG_BANK1_END 0x00000000 -#define CFG_BANK1_ENABLE 0 -#define CFG_BANK2_START 0x00000000 -#define CFG_BANK2_END 0x00000000 -#define CFG_BANK2_ENABLE 0 -#define CFG_BANK3_START 0x00000000 -#define CFG_BANK3_END 0x00000000 -#define CFG_BANK3_ENABLE 0 -#define CFG_BANK4_START 0x00000000 -#define CFG_BANK4_END 0x00000000 -#define CFG_BANK4_ENABLE 0 -#define CFG_BANK5_START 0x00000000 -#define CFG_BANK5_END 0x00000000 -#define CFG_BANK5_ENABLE 0 -#define CFG_BANK6_START 0x00000000 -#define CFG_BANK6_END 0x00000000 -#define CFG_BANK6_ENABLE 0 -#define CFG_BANK7_START 0x00000000 -#define CFG_BANK7_END 0x00000000 -#define CFG_BANK7_ENABLE 0 +#define CONFIG_SYS_BANK0_START 0x00000000 +#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) +#define CONFIG_SYS_BANK0_ENABLE 1 +#define CONFIG_SYS_BANK1_START 0x00000000 +#define CONFIG_SYS_BANK1_END 0x00000000 +#define CONFIG_SYS_BANK1_ENABLE 0 +#define CONFIG_SYS_BANK2_START 0x00000000 +#define CONFIG_SYS_BANK2_END 0x00000000 +#define CONFIG_SYS_BANK2_ENABLE 0 +#define CONFIG_SYS_BANK3_START 0x00000000 +#define CONFIG_SYS_BANK3_END 0x00000000 +#define CONFIG_SYS_BANK3_ENABLE 0 +#define CONFIG_SYS_BANK4_START 0x00000000 +#define CONFIG_SYS_BANK4_END 0x00000000 +#define CONFIG_SYS_BANK4_ENABLE 0 +#define CONFIG_SYS_BANK5_START 0x00000000 +#define CONFIG_SYS_BANK5_END 0x00000000 +#define CONFIG_SYS_BANK5_ENABLE 0 +#define CONFIG_SYS_BANK6_START 0x00000000 +#define CONFIG_SYS_BANK6_END 0x00000000 +#define CONFIG_SYS_BANK6_ENABLE 0 +#define CONFIG_SYS_BANK7_START 0x00000000 +#define CONFIG_SYS_BANK7_END 0x00000000 +#define CONFIG_SYS_BANK7_ENABLE 0 /* * Memory bank enable bitmask, specifying which of the banks defined above * are actually present. MSB is for bank #7, LSB is for bank #0. */ -#define CFG_BANK_ENABLE 0x01 +#define CONFIG_SYS_BANK_ENABLE 0x01 -#define CFG_ODCR 0xff /* configures line driver impedances, */ +#define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */ /* see 8240 book for bit definitions */ -#define CFG_PGMAX 0x32 /* how long the 8240 retains the */ +#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */ /* currently accessed page in memory */ /* see 8240 book for details */ /* SDRAM 0 - 256MB */ -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) /* PCI memory space */ -#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) /* Config addrs, etc */ -#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_DBAT0L CFG_IBAT0L -#define CFG_DBAT0U CFG_IBAT0U -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U -#define CFG_DBAT2L CFG_IBAT2L -#define CFG_DBAT2U CFG_IBAT2U -#define CFG_DBAT3L CFG_IBAT3L -#define CFG_DBAT3U CFG_IBAT3U +#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U +#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U +#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /* * Cache Configuration */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */ +#if defined(CONFIG_CMD_KGDB) +# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif