X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FPMC405.h;h=adbe8a9fba6d2ede7e3ee6d0d1de2d0b184b563e;hb=feaa43f3a8f465cbf01ffa1b23b6b52431819a52;hp=11d6fa767c962208ed52ce6c1cb69f3b58d23abb;hpb=05b47540aae996908e48e10a5ff8b69862aadef3;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h index 11d6fa7..adbe8a9 100644 --- a/include/configs/PMC405.h +++ b/include/configs/PMC405.h @@ -53,29 +53,47 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_NET_MULTI 1 +#undef CONFIG_HAS_ETH1 + #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ + + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_BSP +#define CONFIG_CMD_PCI +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_ELF +#define CONFIG_CMD_DATE +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_I2C +#define CONFIG_CMD_PING +#define CONFIG_CMD_UNIVERSE +#define CONFIG_CMD_EEPROM -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_BSP | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_ELF | \ - CFG_CMD_DATE | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_MII | \ - CFG_CMD_I2C | \ - CFG_CMD_PING | \ - CFG_CMD_UNIVERSE | \ - CFG_CMD_EEPROM ) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ @@ -94,7 +112,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -154,15 +172,24 @@ #define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ #define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0408 /* PCI Device ID: PMC-405 */ +#define CFG_PCI_SUBSYS_DEVICEID_NONMONARCH 0x0408 /* PCI Device ID: Non-Monarch */ +#define CFG_PCI_SUBSYS_DEVICEID_MONARCH 0x0409 /* PCI Device ID: Monarch */ +#define CFG_PCI_SUBSYS_DEVICEID pmc405_pci_subsys_deviceid() + #define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ + +#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */ +#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */ #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#if 1 +#define CFG_PCI_PTM2LA 0xef000000 /* point to internal regs */ +#define CFG_PCI_PTM2MS 0xff000001 /* 16MB, enable */ +#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ +#else /* old mapping */ #define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ #define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - +#endif /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) @@ -183,14 +210,17 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#undef CFG_FLASH_PROTECTION /* don't use hardware protection */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ #define CFG_FLASH_BASE 0xFE000000 #define CFG_FLASH_INCREMENT 0x01000000 +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_PROTECTION 1 /* don't use hardware protection */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE + CFG_FLASH_INCREMENT } +#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ + #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ /* @@ -200,8 +230,8 @@ /* No command line, one static partition, whole device */ #undef CONFIG_JFFS2_CMDLINE #define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 +#define CONFIG_JFFS2_PART_SIZE 0x01b00000 +#define CONFIG_JFFS2_PART_OFFSET 0x00400000 /* mtdparts command line support */ /* Note: fake mtd_id used, no linux mtd map file */ @@ -240,23 +270,13 @@ #define CFG_EEPROM_PAGE_WRITE_ENABLE /*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup */ #define FLASH0_BA 0xFF000000 /* FLASH 0 Base Address */ #define FLASH1_BA 0xFE000000 /* FLASH 1 Base Address */ #define CAN_BA 0xF0000000 /* CAN Base Address */ #define RTC_BA 0xF0000500 /* RTC Base Address */ -#define CF_BA 0xF0100000 /* CompactFlash Base Address */ +#define NVRAM_BA 0xF0200000 /* NVRAM Base Address */ /* Memory Bank 0 (Flash Bank 0) initialization */ #define CFG_EBC_PB0AP 0x92015480 @@ -270,9 +290,11 @@ #define CFG_EBC_PB2AP 0x03000440 /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */ #define CFG_EBC_PB2CR CAN_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ -/* Memory Bank 3 (CompactFlash IDE, FPGA internal) initialization */ -#define CFG_EBC_PB3AP 0x010059C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB3CR CF_BA | 0x1A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ +/* Memory Bank 3 -> unused */ + +/* Memory Bank 4 (NVRAM) initialization */ +#define CFG_EBC_PB4AP 0x03000440 /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */ +#define CFG_EBC_PB4CR NVRAM_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ /*----------------------------------------------------------------------- * FPGA stuff @@ -290,6 +312,15 @@ #define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ /*----------------------------------------------------------------------- + * GPIOs + */ +#define CFG_NONMONARCH (0x80000000 >> 14) /* GPIO24 */ +#define CFG_XEREADY (0x80000000 >> 15) /* GPIO15 */ +#define CFG_INTA_FAKE (0x80000000 >> 19) /* GPIO19 */ +#define CFG_SELF_RST (0x80000000 >> 21) /* GPIO21 */ +#define CFG_REV1_2 (0x80000000 >> 23) /* GPIO23 */ + +/*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in data cache) */