X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FPM856.h;h=9d535b6bb47eafd971f67118e2408cd17ef35aa0;hb=0e8d158664a913392cb01fb11a948d83f72e105e;hp=b2cf06000fda0a3ae53d2680934bdacbe8dfb096;hpb=28ac6719108e989429de2b3dfa90312ba7c4d27b;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/PM856.h b/include/configs/PM856.h
index b2cf060..9d535b6 100644
--- a/include/configs/PM856.h
+++ b/include/configs/PM856.h
@@ -45,11 +45,6 @@
 #define CONFIG_PCI
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
-#undef  CONFIG_SPD_EEPROM		/* do not use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_ECC			/* only for ECC DDR module */
-#define CONFIG_DDR_DLL			/* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
-#define CONFIG_MEM_INIT_VALUE		0xDEADBEEF
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
@@ -97,33 +92,36 @@
 #define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
+/* DDR Setup */
+#define CONFIG_FSL_DDR1
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#undef CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#undef CONFIG_DDR_SPD
+#define CONFIG_DDR_DLL                      /* possible DLL fix needed */
+#define CONFIG_DDR_ECC			    /* only for ECC DDR module */
 
-/*
- * DDR Setup
- */
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CFG_DDR_SDRAM_BASE	0x00000000
 #define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
 
-#if defined(CONFIG_SPD_EEPROM)
-    /*
-     * Determine DDR configuration from I2C interface.
-     */
-    #define SPD_EEPROM_ADDRESS	0x58		/* DDR DIMM */
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
 
-#else
-    /*
-     * Manually set up DDR parameters
-     */
-    #define CFG_SDRAM_SIZE	256		/* DDR is 256 MB */
-    #define CFG_DDR_CS0_BNDS	0x0000000f	/* 0-256MB */
-    #define CFG_DDR_CS0_CONFIG	0x80000102
-    #define CFG_DDR_TIMING_1	0x47444321
-    #define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
-    #define CFG_DDR_CONTROL	0xc2008000	/* unbuffered,no DYN_PWR */
-    #define CFG_DDR_MODE	0x00000062	/* DLL,normal,seq,4/2.5 */
-    #define CFG_DDR_INTERVAL	0x045b0100	/* autocharge,no open page */
-#endif
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x58	/* CTLR 0 DIMM 0 */
 
+/* Manually set up DDR parameters */
+#define CFG_SDRAM_SIZE	256		/* DDR is 256 MB */
+#define CFG_DDR_CS0_BNDS	0x0000000f	/* 0-256MB */
+#define CFG_DDR_CS0_CONFIG	0x80000102
+#define CFG_DDR_TIMING_1	0x47444321
+#define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
+#define CFG_DDR_CONTROL	0xc2008000	/* unbuffered,no DYN_PWR */
+#define CFG_DDR_MODE	0x00000062	/* DLL,normal,seq,4/2.5 */
+#define CFG_DDR_INTERVAL	0x045b0100	/* autocharge,no open page */
 
 /*
  * SDRAM on the Local Bus
@@ -295,15 +293,15 @@
  * Environment
  */
 #ifndef CFG_RAMBOOT
-  #define CFG_ENV_IS_IN_FLASH	1
-  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x80000)
-  #define CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
-  #define CFG_ENV_SIZE		0x2000
+  #define CONFIG_ENV_IS_IN_FLASH	1
+  #define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - 0x80000)
+  #define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
+  #define CONFIG_ENV_SIZE		0x2000
 #else
   #define CFG_NO_FLASH		1	/* Flash is not usable now */
-  #define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
-  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
-  #define CFG_ENV_SIZE		0x2000
+  #define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+  #define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+  #define CONFIG_ENV_SIZE		0x2000
 #endif
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */