X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FPM854.h;h=1beee0fb4c67d76987eb9e5f83bec2ed9d048b66;hb=0e8d158664a913392cb01fb11a948d83f72e105e;hp=bf7eb8e97a776b98f35211160b17dc8c7fe07a14;hpb=384cc687445b34241fcc8b31bbb7aa9fc252dd90;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/PM854.h b/include/configs/PM854.h index bf7eb8e..1beee0f 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -44,11 +44,8 @@ #define CONFIG_PCI #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE -#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_DDR_DLL /* possible DLL fix needed */ -#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ /* * sysclk for MPC85xx @@ -89,35 +86,40 @@ */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ -/* - * DDR Setup - */ -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +/* DDR Setup */ +#define CONFIG_FSL_DDR1 +#undef CONFIG_FSL_DDR_INTERACTIVE +#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ +#undef CONFIG_DDR_SPD +#define CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_DDR_ECC /* only for ECC DDR module */ + +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + +#define CFG_DDR_SDRAM_BASE 0x00000000 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE +#define CONFIG_VERY_BIG_RAM -#if defined(CONFIG_SPD_EEPROM) - /* - * Determine DDR configuration from I2C interface. - */ - #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 2 -#else - /* - * Manually set up DDR parameters - */ - #define CFG_SDRAM_SIZE 256 /* DDR is 256 MB */ - #define CFG_DDR_CS0_BNDS 0x0000000f /* 0-256MB */ - #define CFG_DDR_CS0_CONFIG 0x80000102 - #define CFG_DDR_TIMING_1 0x47444321 - #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ - #define CFG_DDR_CONTROL 0xc2008000 /* unbuffered,no DYN_PWR */ - #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ - #define CFG_DDR_INTERVAL 0x045b0100 /* autocharge,no open page */ -#endif +/* I2C addresses of SPD EEPROMs */ +#define SPD_EEPROM_ADDRESS 0x58 /* CTLR 0 DIMM 0 */ +/* Manually set up DDR parameters */ +#define CFG_SDRAM_SIZE 256 /* DDR is 256 MB */ +#define CFG_DDR_CS0_BNDS 0x0000000f /* 0-256MB */ +#define CFG_DDR_CS0_CONFIG 0x80000102 +#define CFG_DDR_TIMING_1 0x47444321 +#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ +#define CFG_DDR_CONTROL 0xc2008000 /* unbuffered,no DYN_PWR */ +#define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ +#define CFG_DDR_INTERVAL 0x045b0100 /* autocharge,no open page */ /* * SDRAM on the Local Bus @@ -144,19 +146,20 @@ #undef CFG_RAMBOOT #endif +#define CONFIG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_FLASH_EMPTY_INFO #undef CONFIG_CLOCKS_IN_MHZ - /* * Local Bus Definitions */ - #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ - + #define CONFIG_L1_INIT_RAM #define CFG_INIT_RAM_LOCK 1 @@ -190,12 +193,16 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 /* * EEPROM configuration @@ -232,8 +239,9 @@ #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP +#define CONFIG_EEPRO100 +#define CONFIG_E1000 +#undef CONFIG_TULIP #if !defined(CONFIG_PCI_PNP) #define PCI_ENET0_IOADDR 0xe0000000 @@ -254,19 +262,27 @@ #endif #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC2 1 -#define TSEC1_PHY_ADDR 2 -#define TSEC2_PHY_ADDR 3 +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT #define CONFIG_MPC85XX_FEC 1 -#define FEC_PHY_ADDR 1 +#define CONFIG_MPC85XX_FEC_NAME "FEC" +#define FEC_PHY_ADDR 3 #define FEC_PHYIDX 0 +#define FEC_FLAGS 0 -#define CONFIG_ETHPRIME "MOTO ENET0" +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC0" +#define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 1 #define CONFIG_HAS_ETH2 1 @@ -277,55 +293,50 @@ * Environment */ #ifndef CFG_RAMBOOT - #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x80000) - #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ - #define CFG_ENV_SIZE 0x2000 + #define CONFIG_ENV_IS_IN_FLASH 1 + #define CONFIG_ENV_ADDR (CFG_MONITOR_BASE - 0x80000) + #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CONFIG_ENV_SIZE 0x2000 #else #define CFG_NO_FLASH 1 /* Flash is not usable now */ - #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) - #define CFG_ENV_SIZE 0x2000 + #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CONFIG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CONFIG_ENV_SIZE 0x2000 #endif #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_DATE +#define CONFIG_CMD_EEPROM + +#if defined(CONFIG_PCI) + #define CONFIG_CMD_PCI +#endif + #if defined(CFG_RAMBOOT) - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_PCI \ - | CFG_CMD_I2C) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_LOADS)) - #else - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_LOADS)) - #endif -#else - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_EEPROM \ - | CFG_CMD_DATE \ - | CFG_CMD_PCI \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) - #else - #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_EEPROM \ - | CFG_CMD_DATE \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) - #endif + #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_LOADS #endif -#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -336,7 +347,7 @@ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -355,13 +366,6 @@ */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#endif - /* * Internal Definitions * @@ -370,7 +374,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif @@ -387,13 +391,13 @@ #define CONFIG_ETH2ADDR 00:40:42:01:00:02 #endif -#define CONFIG_IPADDR 192.168.0.103 -#define CONFIG_HOSTNAME PM854 -#define CONFIG_ROOTPATH /opt/eldk30/ppc_82xx -#define CONFIG_BOOTFILE uImage +#define CONFIG_ROOTPATH /opt/eldk/ppc_85xx +#define CONFIG_BOOTFILE pm854/uImage -#define CONFIG_SERVERIP 192.168.0.54 +#define CONFIG_HOSTNAME pm854 +#define CONFIG_IPADDR 192.168.0.103 +#define CONFIG_SERVERIP 192.168.0.64 #define CONFIG_GATEWAYIP 192.168.0.1 #define CONFIG_NETMASK 255.255.255.0 @@ -408,7 +412,7 @@ "netdev=eth0\0" \ "consoledev=ttyS0\0" \ "ramdiskaddr=400000\0" \ - "ramdiskfile=uRamdisk\0" + "ramdiskfile=pm854/uRamdisk\0" #define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \