X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FP2041RDB.h;h=e196f3ce33ab32cbc97fbf0104eb2f2ca749960a;hb=c18b103657d9541305a45a1fb21f979c317fba49;hp=8e71fdfecd0e779bcce6598b59a0cc8f8b8c0417;hpb=8e5f0497c8a8ab9bd7314737f2edb4711733b6fe;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 8e71fdf..e196f3c 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -1,7 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2011-2012 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -28,11 +27,6 @@ /* High Level Configuration Options */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_MP /* support multiple processors */ - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff40000 -#endif #ifndef CONFIG_RESET_VECTOR_ADDRESS #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc @@ -54,30 +48,16 @@ #define CONFIG_ENV_OVERWRITE -#ifndef CONFIG_MTD_NOR_FLASH -#else -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE -#endif - #if defined(CONFIG_SPIFLASH) - #define CONFIG_SYS_EXTRA_ENV_RELOC - #define CONFIG_ENV_SPI_BUS 0 - #define CONFIG_ENV_SPI_CS 0 - #define CONFIG_ENV_SPI_MAX_HZ 10000000 - #define CONFIG_ENV_SPI_MODE 0 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ #define CONFIG_ENV_SECT_SIZE 0x10000 #elif defined(CONFIG_SDCARD) - #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_FSL_FIXED_MMC_LOCATION #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_OFFSET (512 * 1658) #elif defined(CONFIG_NAND) -#define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) @@ -115,7 +95,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00400000 -#define CONFIG_SYS_ALT_MEMTEST /* * Config the L3 Cache as L3 SRAM @@ -263,9 +242,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} -#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ -#define CONFIG_MISC_INIT_R - #define CONFIG_HWCONFIG /* define to use L1 as initial stack */ @@ -297,7 +273,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); * open - index 2 * shorted - index 1 */ -#define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) @@ -371,8 +346,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); /* * eSPI - Enhanced SPI */ -#define CONFIG_SF_DEFAULT_SPEED 10000000 -#define CONFIG_SF_DEFAULT_MODE 0 /* * General PCI @@ -437,7 +410,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* Qman/Bman */ -#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ #define CONFIG_SYS_BMAN_NUM_PORTALS 10 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 #ifdef CONFIG_PHYS_64BIT @@ -479,7 +451,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); * env is stored at 0x100000, sector size is 0x10000, ucode is stored after * env, so we got 0x110000. */ -#define CONFIG_SYS_QE_FW_IN_SPIFLASH #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 #elif defined(CONFIG_SDCARD) /* @@ -487,10 +458,8 @@ unsigned long get_board_sys_clk(unsigned long dummy); * about 825KB (1650 blocks), Env is stored after the image, and the env size is * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ -#define CONFIG_SYS_QE_FMAN_FW_IN_MMC #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) #elif defined(CONFIG_NAND) -#define CONFIG_SYS_QE_FMAN_FW_IN_NAND #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* @@ -500,17 +469,14 @@ unsigned long get_board_sys_clk(unsigned long dummy); * slave SRIO or PCIE outbound window->master inbound window-> * master LAW->the ucode address in master's memory space. */ -#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 #else -#define CONFIG_SYS_QE_FMAN_FW_IN_NOR #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #ifdef CONFIG_SYS_DPAA_FMAN -#define CONFIG_FMAN_ENET #define CONFIG_PHYLIB_10G #define CONFIG_PHY_VITESSE #define CONFIG_PHY_TERANETICS @@ -552,7 +518,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0 #define CONFIG_SYS_TBIPA_VALUE 8 -#define CONFIG_MII /* MII PHY management */ #define CONFIG_ETHPRIME "FM1@DTSEC1" #endif @@ -578,7 +543,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #endif #ifdef CONFIG_MMC -#define CONFIG_FSL_ESDHC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT #endif @@ -586,9 +550,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ /*